Hybridized MAPS with an in-pixel A-to-D conversion readout ASIC

Carini, G.; Deptuch, G.; Fahim, Farah; Kadłubowski, Łukasz A.; Klabbers, P.; Lauxtermann, Stefan; Petterson, Per-Olov; Zimmerman, T.

doi:10.1016/j.nima.2019.03.091

Cited by 9 publications

(5 citation statements)

References 7 publications

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“…Therefore, we decided to utilize a novel recording channel architecture supported by a modern nanometer CMOS process. This is a continuation of previous work on the development of readout integrated circuits for hybrid pixel detectors [10][11][12][13]. There are many different time measurement approaches [7][8][9][14][15][16]] and here we decided to use Vernier TDC architecture with two ring oscillators [5,6] that may offer resolution even on the order of 5.1 ps and in that way should be suitable for this project.…”

Section: Introductionmentioning

confidence: 80%

Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS

Kadłubowski¹,

Kmon²

2021

J. Inst.

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The paper describes a design of a prototype chip in 28 nm CMOS technology, consisting of 8 × 4 pixels with 50 μm pitch, dedicated for the precise measurement of Time-of-Arrival (ToA) and Time-over-Threshold (ToT) with a resolution within the picosecond range. To address this requirement, in-pixel Vernier time-to-digital converter (TDC) has been implemented, which utilizes two ring oscillators per pixel. Overall chip architecture is introduced as well as pixel architecture and selected simulation results. The pixel consists of a recording channel and TDC part. The recording channel is composed of an inverter-based front-end amplifier with Zimmerman feedback, a discriminator, a calibration block and a threshold setting block. TDC part includes two ring oscillators together with their calibration blocks and additional logic with counters/shift registers that allow for precise ToA measurement (using Vernier method) as well as ToT measurement (using one of the oscillators). Alternatively, single photon counting (SPC) mode can be used. Frequency of oscillators is set in three steps. First, two global 8-bit digital-to-analog converters (DACs) are used for initial setting of all ring oscillators. Then, per-oscillator capacitance bank and 6-bit DAC are used for fine setting. Simulation results of core blocks suggest that the ToA resolution on the order of tens of picoseconds may be achieved. The chips are already fabricated and are currently being prepared for measurements.

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Section: Introductionmentioning

confidence: 80%

Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS

Kadłubowski¹,

Kmon²

2021

J. Inst.

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“…The first is a 192  192 pixel array [39] in 130 nm LP-CMOS, with both full frame as well as zero-suppressed readout capabilities. The second is a 64  64 pixel array in 65 nm LP-CMOS [7], exclusively with full-frame readout, which does not require the address generation logic. The test results presented in this section are for this second ROIC, which is the only one available so far.…”

Section: Resultsmentioning

confidence: 99%

“…As pixel detectors have evolved over the last few decades, the readout of the pixels has itself evolved from simple analog readouts to fast digital readouts enabling higher data frame rates. Typical inpixel digital measurements include counting the number of incoming photons [1,2,3], measuring the time of arrival of the photon [4,5] or analog-to-digital conversion of accumulated photons [6,7,8] within a given time frame or integration window. It is generally desirable for these detectors to be operated continuously without any deadtime such that when new information is being recorded in the current time frame, simultaneously the previous information is being sent off to the data acquisition system.…”

Section: Introductionmentioning

confidence: 99%

A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree

Fahim

Joshi

Ogrenci-Memik

et al. 2020

IEEE Trans. VLSI Syst.

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A low-power, high-speed arbitration tree for pixel detector readout is presented. The synchronized, binary tree priority encoder establishes a position dependent priority list at the start of every time frame. Pixels that indicate the presence of data for readout, are sequentially granted access to a shared bus for data transfer to the periphery, without the use of an additional global strobe signal. It can be used for either full frame imaging or zero-suppressed readout, in which case it can simultaneously generate the pixel address. To increase the readout frame rate, the pixel array is subdivided into two halves, which allows interleaved latching of data at the output serializer. The design was implemented in a 65 nm LP-CMOS process for the readout of a 64  64 pixel array. Measurement results demonstrate a deadtimeless, full frame imaging rate of ~50 kfps, achieved with a dedicated output for every (32  32) 1024 pixels and for a pixel data packet of 11 bits, with no bit errors detected over 1000 frames. The measured energy per bit is 0.94 pJ.

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“…Implementing a high-speed and high-precision single-slope pixel-level ADC would require distributing a high-speed clock and a high-quality ramping signal throughout the entire pixel matrix, which remains a significant design challenge. Successive approximation register (SAR) ADC also emerges as pixel-level ADC in some recent works [14][15][16], but high resolution implementation with tight layout and consistent performance among massive parallel channels still need to be demonstrated.…”

Section: Introductionmentioning

confidence: 99%

An 11-bit SAR ADC for high frame rate and high-dynamic X-ray imaging at future XFELs

Ji,

Ju,

et al. 2024

J. Inst.

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The paper presents the design and test results of an 11-bit successive approximation register (SAR) ADC, suitable for massive on-chip integration in a pixel readout chip. The objective is to establish new digital readout architectures for X-ray pixel detectors at future X-ray free electron laser (XFEL) facilities, enabling high frame rates and a high dynamic range simultaneously. The prototype chip has been designed and fabricated in a 130 nm CMOS process, with the core circuit occupying an area of ~ 0.034 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.78/-0.78 LSB and +0.58/-0.52 LSB, respectively. The signal-to-noise-and-distortion ratio (SINAD) is 61.6 dB at 2 MS/s, achieving an effective number of bit (ENOB) of ~ 9.94-bit. The core circuit power consumption is 47 μW at 2 MS/s with a 1.2 V supply.

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Hybridized MAPS with an in-pixel A-to-D conversion readout ASIC

Cited by 9 publications

References 7 publications

Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS

Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS

A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree

An 11-bit SAR ADC for high frame rate and high-dynamic X-ray imaging at future XFELs

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