Hybrid transactional memory

Damron, Peter; Fedorova, Alexandra; Lev, Yossi; Luchangco, Victor; Moir, Mark; Nussbaum, Daniel A.

doi:10.1145/1168857.1168900

Cited by 265 publications

(115 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…On the contrary Hardware Transactional Memory systems are fast for transactions that fit into the restricted hardware [8], [9], [10]. Further, hybrid approaches, combining hardware and software to accelerate execution and lift the limits of the hardware have been researched [11], [12], [13], [14]. The only paper that described an early experience with a commercial hardware transactional memory implementation published in a major conference, to our knowledge, is by Dice et al [15].…”

Section: Background and Related Workmentioning

confidence: 99%

What Scientific Applications can Benefit from Hardware Transactional Memory?

Schindewolf¹,

Bihari²,

Gyllenhaal³

et al. 2012

View full text Add to dashboard Cite

Abstract-Achieving efficient and correct synchronization of multiple threads is a difficult and error-prone task at small scale and, as we march towards extreme scale computing, will be even more challenging when the resulting application is supposed to utilize millions of cores efficiently. Transactional Memory (TM) is a promising technique to ease the burden on the programmer, but only recently has become available on commercial hardware in the new Blue Gene/Q system and hence the real benefit for realistic applications has not been studied, yet.This paper presents the first performance results of TM embedded into OpenMP on a prototype system of BG/Q and characterizes code properties that will likely lead to benefits when augmented with TM primitives. We first, study the influence of thread count, environment variables and memory layout on TM performance and identify code properties that will yield performance gains with TM. Second, we evaluate the combination of OpenMP with multiple synchronization primitives on top of MPI to determine suitable task to thread ratios per node. Finally, we condense our findings into a set of best practices. These are applied to a Monte Carlo Benchmark and a Smoothed Particle Hydrodynamics method. In both cases an optimized TM version, executed with 64 threads on one node, outperforms a simple TM implementation. MCB with optimized TM yields a speedup of 27.45 over baseline.

show abstract

Section: Background and Related Workmentioning

confidence: 99%

What Scientific Applications can Benefit from Hardware Transactional Memory?

Schindewolf¹,

Bihari²,

Gyllenhaal³

et al. 2012

View full text Add to dashboard Cite

show abstract

“…No knowledge about HEI or TM semantics is incorporated at this point. An example of such a system is HyTM [17]. The following are some necessary conditions for HEI to function on top of hardware TM.…”

Section: Enabling Hei With Hardware Tmmentioning

confidence: 99%

Hardware support for enforcing isolation in lock-based parallel programs

Ratanaworabhan

Burtscher

Kirovski

et al. 2012

Proceedings of the 26th ACM International Conference on Supercomputing

View full text Add to dashboard Cite

When lock-based parallel programs execute on conventional multicore hardware, faulty software can cause hard-to-debug race conditions in critical sections that violate the contract between locks and their protected shared variables. This paper proposes new hardware support for enforcing isolation of critical section execution. It can detect and tolerate races, allowing programs to execute race-free. Our hardware scheme targets the existing large code base of lockedbased parallel programs written in type unsafe languages such as C and C++. Our approach works directly on unmodified executables. An evaluation of 13 programs from the SPLASH2 and PARSEC suites shows that the cost of the additional hardware and the impact on the overall execution time is minimal for these applications. Our mechanism is complementary to hardware transactional memory in that it uses similar structures but focuses on enhancing the reliability of existing lock-based programs.

show abstract

“…Hybrid TMs [8,16] allow hardware to handle common-case bounded transactions, and fall back to software for transactions that overflow time and space resources. Hybrid TMs must maintain metadata compatible with the fallback STM and use policies compatible with the underlying HTM.…”

Section: Related Workmentioning

confidence: 99%

“…The mechanisms required for conflict detection, conflict management, and version management can be implemented in hardware (HTM) [1,12,14,23,24], software (STM) [9,10,13,19,25], or some hybrid of the two (HyTM) [8,16,22,30]. Full hardware systems are typically inflexible in policy, with fixed choices for eagerness of conflict management, strategies for conflict arbitration and back-off, and eagerness of versioning.…”

Section: Introductionmentioning

confidence: 99%

Flexible Decoupled Transactional Memory Support

Shriraman

Dwarkadas

Scott

2008

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

A high-concurrency transactional memory (TM) implementation needs to track concurrent accesses, buffer speculative updates, and manage conflicts. We present a system, FlexTM (FLEXible Transactional Memory), that coordinates four decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary tables (CSTs), which identify the threads with which conflicts have occurred; Programmable Data Isolation, which maintains speculative updates in the local cache and employs a thread-private buffer (in virtual memory) in the rare event of overflow; and Alert-On-Update, which selectively notifies threads about coherence events. All mechanisms are softwareaccessible, to enable virtualization and to support transactions of arbitrary length. FlexTM allows software to determine when to manage conflicts (either eagerly or lazily), and to employ a variety of conflict management and commit protocols. We describe an STM-inspired protocol that uses CSTs to manage conflicts in a distributed manner (no global arbitration) and allows parallel commits.In experiments with a prototype on Simics/GEMS, FlexTM exhibits ∼5× speedup over high-quality software TM, with no loss in policy flexibility. Its distributed commit protocol is also more efficient than a central hardware manager. Our results highlight the importance of flexibility in determining when to manage conflicts: lazy maximizes concurrency and helps to ensure forward progress while eager provides better overall utilization in a multi-programmed system.

show abstract

Hybrid transactional memory

Cited by 265 publications

References 21 publications

What Scientific Applications can Benefit from Hardware Transactional Memory?

What Scientific Applications can Benefit from Hardware Transactional Memory?

Hardware support for enforcing isolation in lock-based parallel programs

Flexible Decoupled Transactional Memory Support

Contact Info

Product

Resources

About