Hybrid system level power consumption estimation for FPGA-based MPSoC

Rethinagiri, Santhosh Kumar; Atitallah, Rabıe Ben; Niar, Smaïl; Senn, Eric; Dekeyser, Jean-Luc

doi:10.1109/iccd.2011.6081403

Cited by 13 publications

(4 citation statements)

References 10 publications

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“…Another method is addressed in [14], where power models are represented by an analytical function or by a table of consumption values, which depend on a set of parameters such as cache miss rate and pipeline stall rate. These models are extended in [15] to address the OMAP (ARM + DSP) platform. These approaches may have a good accuracy in some cases, but are quite design specific.…”

Section: Background and Related Workmentioning

confidence: 99%

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

Najem

Benoit

Ahmad

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The emergence of power as a first-class design constraint has fueled the proposal of a growing number of optimization techniques, seeking the best tradeoff to reach the maximum energy efficiency. Effective adaptation strategies depend critically on the monitoring method as an incorrect assessment of the system's state will result in poor decision making. Yet it is indeed a fundamental issue: how to get a precise estimation of the system's state, and especially in a cost-effective way? We address this question for the self-observation of the power consumption. We develop a method that combines several data mining algorithms to monitor the toggling activity on a few relevant signals selected at the register transfer-level. Our approach is based on a generic flow that is able to produce a power model for any register transfer level (RTL) circuit on any technology. This contribution is evaluated on a system on chip RTL model implemented on an field-programmable gate array technology. The experiments demonstrate that the proposed method achieves the accuracy of analog power sensors (error lower than 1%) at a finer granularity and in a cost-effective way. Index Terms-Data mining, design-time method, fieldprogrammable gate array (FPGA), power modeling, register transfer-level, system on chip (SoC) monitoring.

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Section: Background and Related Workmentioning

confidence: 99%

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

Najem

Benoit

Ahmad

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…One of the academic methods of hybrid consumption estimation for systems-on-chip is HSL [66]. It was published in 2011 as a founded collaboration between the University of Lille, the University of Valenciennes and the University of South Brittany.…”

Section: B5 Hybrid System Level Power Consumption Estimation (Hsl)mentioning

confidence: 99%

SoC Power Consumption Estimation at High Level of Abstraction: A Survey Study

Alali¹,

Hariti²,

Sadik³

et al. 2022

IJETAE

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Abstract—As electric energy consumption becomes a more pressing concern in System-on-a-Chip (SOC) design, accurate and efficient power analysis and estimation at all levels of abstraction throughout the design phase is becoming increasingly important in order to achieve low power without an expensive redesign process. This study examines dynamic power and leaky power analysis and estimation strategies for SOC design at several design levels that have recently been proposed, with the goal of presenting a unified view of power estimation methodologies at all design levels of abstraction, focusing especially on the high level. Keywords— System on Chip; Energy estimation; SoC modelling; Accuracy; High level of abstraction.

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“…In [11], the development of multi-level power models enable to estimate power of FPGA designs all along the design development in function of the available information at each level. Power models are built using the Functional Level Power Analysis (FLPA) methodology [12], [13].Another power modelling approach is described in [14]. The methodology called FLPAM, allows to model area and power of FPGA-based Custom IP cores.…”

Section: Related Workmentioning

confidence: 99%

Dynamic power evaluation of LTE wireless baseband processing on FPGA

Lorandel

Prévotet

Hélard

2015

2015 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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Mobile networks and user equipments continuously evolve to circumvent the data traffic growth and the increasing number of users. However, the complexity and heterogeneity of such systems (3G, LTE, LTE-A, etc.) makes power one of the most critical metric. In this context, power estimation has become an unavoidable task in the design process. In this paper, a dynamic power estimation methodology for FPGA-based systems is presented. It aims at providing accurate and fast power estimations of an entire system prior to its implementation. It also aims at making design space exploration easier. We introduce an innovative scenario-level in order to facilitate the comparison of domain-specific systems. We show the effectiveness of our approach on several LTE baseband configurations which leads to a low absolute error, compared to classic estimations. It also exhibits a high speed-up factor which is determinant during design space exploration.

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Hybrid system level power consumption estimation for FPGA-based MPSoC

Cited by 13 publications

References 10 publications

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

SoC Power Consumption Estimation at High Level of Abstraction: A Survey Study

Dynamic power evaluation of LTE wireless baseband processing on FPGA

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