Hybrid On-Line Self-Test Strategy for Dual-Core Lockstep Processors

Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs

“…With conventional design methods [12]- [15], [19], (b-1) and (b-2) are easily embeddable in an FPGA; however, (b-3) is insufficient. Regarding (b-3), the issues with implementing comparators in FPGAs are as follows.…”

“…2) The probability of short circuit for wiring in FPGAs is higher than that in ASICs due to the SEU in configuration memory (CRAM). There are cases in which some faults are missed because the method discussed in a previous study [12] is only considered "stack-at faults." Fault models for mapping a circuit to an LUT in an FPGA have been reported [20], [21].…”

“…TSC is indispensable for highly reliable systems, especially regarding safety applications [12], [13], [19]. TSC is defined as follows [2].…”

“…Our method is applicable to the software-compare method discussed in a previous study [12] when we map the architecture in that study to an FPGA. First, the test patterns expand when the applied LUT-based design complies with our method.…”

“…To develop self-checking LSIs, another possible method is duplicating functional blocks and verifying the output of these blocks using a self-checking data-compare mechanism through ad hoc design. Therefore, intrachip redundancy is commonly used for achieving dependability [12], [13]. Totally selfchecking (TSC) comparators with an online fault injection method for intrachip redundancy were proposed [14], [15].…”