Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL

Abstract

A great deal of effort has recently been devoted to extending the usage of memristor technology from memory to computing. Memristor-based logic design is an emerging concept that targets efficient computing systems. Several logic families have evolved, each with different attributes. Memristor Ratioed Logic (MRL) has been recently introduced as a hybrid memristor–CMOS logic family. MRL requires an efficient design strategy that takes into consideration the implementation phase. This paper presents a novel MRL-based crossbar design: X-MRL. The proposed structure combines the density and scalability attributes of memristive crossbar arrays and the opportunity of their implementation at the top of CMOS layer. The evaluation of the proposed approach is performed through the design of an X-MRL-based full adder. The design is presented with its layout and corresponding simulation results using the Cadence Virtuoso toolset and CMOS 65nm process. The comparison with a pure CMOS implementation is promising in terms of the area, as our approach exhibits a 44.79% area reduction. Moreover, the combined Energy.Delay metric demonstrates a significant improvement (between ×5.7 and ×31) with respect to the available literature.

Design of memristor-based combinational logic circuits

“…For example, [32] has the best performance using MAGIC method in the table, with 18.8% lower energy and 19.7% lower delay per step than ours, but it needs more steps to implement, so our energy-delay product is 90.4% lower. While [33] has a lower energy-delay product by 11.8% compared to ours, it comes at the cost of an increased device count, which is 38.4% higher than our method. Taking all factors into consideration, our work has a certain advantage in balancing circuit performance and device count.…”