Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric

Khasanvis, Santosh; Habib, K. M. Masum; Rahman, Mostafizur; Narayanan, Pritish; Lake, Roger K.; Moritz, Csaba Andras

doi:10.1109/nanoarch.2011.5941503

Cited by 14 publications

(13 citation statements)

References 36 publications

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“…Our previous work explored binary random access memory circuit using xGNR latch as the memory core, and access transistors for writing and reading data [Khasanvis et al 2011]. This could also be used as a ternary memory cell [Khasanvis et al 2012].…”

Section: Application Of Xgnr Device In a Multistate Memory Elementmentioning

confidence: 99%

“…A cross-technology heterogeneous implementation is used between CMOS and graphene [Khasanvis et al 2011], as shown in Fig. 11.…”

Section: Physical Implementationmentioning

confidence: 99%

“…Our previous work has explored a binary memory circuit using this xGNR device [Khasanvis et al 2011], which could also function as ternary memory [Khasanvis et al 2012] but did not scale further. In this paper, we present a scaling approach that is different from physical scaling, where the number of bits stored in a single cell can be increased.…”

Section: Introductionmentioning

confidence: 99%

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Low-Power Heterogeneous Graphene Nanoribbon-CMOS Multistate Volatile Memory Circuit

Khasanvis

Habib

Rahman

et al. 2015

J. Emerg. Technol. Comput. Syst.

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Graphene is an emerging nanomaterial believed to be a potential candidate for post-Si nanoelectronics due to its exotic properties. Recently, a new graphene nanoribbon crossbar (xGNR) device was proposed which exhibits negative differential resistance (NDR). In this article, a multistate memory design is presented that can store multiple bits in a single cell enabled by this xGNR device, called graphene nanoribbon tunneling random access memory (GNTRAM). An approach to increase the number of bits per cell is explored alternative to physical scaling to overcome CMOS SRAM limitations. A comprehensive design for quaternary GNTRAM is presented as a baseline, implemented with a heterogeneous integration between graphene and CMOS. Sources of leakage and approaches to mitigate them are investigated. This design is extensively benchmarked against 16nm CMOS SRAMs and 3T DRAM. The proposed quaternary cell shows up to 2.27× density benefit versus 16nm CMOS SRAMs and 1.8× versus 3T DRAM. It has comparable read performance and is power efficient up to 1.32× during active period and 818× during standby against high-performance SRAMs. Multistate GNTRAM has the potential to realize high-density low-power nanoscale embedded memories. Further improvements may be possible by using graphene more extensively, as graphene transistors become available in the future.

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Section: Application Of Xgnr Device In a Multistate Memory Elementmentioning

confidence: 99%

“…A cross-technology heterogeneous implementation is used between CMOS and graphene [Khasanvis et al 2011], as shown in Fig. 11.…”

Section: Physical Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low-Power Heterogeneous Graphene Nanoribbon-CMOS Multistate Volatile Memory Circuit

Khasanvis

Habib

Rahman

et al. 2015

J. Emerg. Technol. Comput. Syst.

Self Cite

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“…The current dimension shrinkage trend in CMOS technology has led to the development of various nano-devices such as Doped/Schottky Barrier Silicon Nanowire FETs (SiNWFETs), Carbon Nanotube FETs (CNTFETs) and Graphenebased devices exhibiting short-channel effect immunity, greater electrostatic control, and lower leakage [1], [2], [3]. However, fabrication-induced Process Variations (PVs) on device and circuit characteristics are a growing challenge with ongoing feature size downscaling.…”

Section: Introductionmentioning

confidence: 99%

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection

Mohammadi

Gaillardon

Yazdani

et al. 2014

Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures

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Abstract-With growing concern about process variation in deeply nano-scaled technologies, parameterized device and circuit modeling is becoming very important for design and verification. However, the high dimensionality of parameter space is a serious modeling challenge for emerging VLSI technologies, where the models are increasingly more complex. In this paper, we propose and validate a feature selection method to reduce the circuit modeling complexity associated with high parameter dimensionality. Despite the commonly used methods such as Principal Component Analysis (PCA) and Independent Component Analysis (ICA), this method is capable of dealing with mixed Gaussian and non-Gaussian parameters, and performs a parameter selection in the input space rather than creating a new space. By considering non-linear dependencies among input parameters and outputs, the method results in an effective parameter selection. The application of this method is demonstrated in digital circuit timing analysis to effectively reduce the number of simulations. The experimental results on Double-Gate Silicon NanoWire FET (DG-SiNWFET) technology indicate 2.5× speed up in timing variation analysis of the ISCAS89-s27 benchmark with a controlled average error bound of 9.4%.

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“…These nanoscale computing systems are based on novel nanostructures, such as nanowires [1], [2], carbon nanotubes [3], graphene [4], [5], magneto electric devices [6], [7], [8], etc. Their manufacturing approaches incorporate unconventional (e.g., self-assembly, nano-imprint) and conventional (e.g., deposition, etching, and lithography) process steps.…”

Section: Introductionmentioning

confidence: 99%