Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU

Kim, Dongki; Lee, Sungkwang; Chung, JaeWoong; Kim, Dae Hyun; Woo, Dong Hyuk; Yoo, Sungjoo; Lee, Sunggu

doi:10.1145/2228360.2228519

Cited by 29 publications

(15 citation statements)

References 9 publications

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“…Alternatively, PCM devices can be used as memory [Kim et al 2012;Lee et al 2009;Mogul et al 2009;Qureshi et al 2009Qureshi et al , 2012. The main challenge in using PCM devices as a memory device is that writes are too slow.…”

Section: Background and Related Workmentioning

confidence: 99%

Evaluating Phase Change Memory for Enterprise Storage Systems

et al. 2014

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Storage systems based on Phase Change Memory (PCM) devices are beginning to generate considerable attention in both industry and academic communities. But whether the technology in its current state will be a commercially and technically viable alternative to entrenched technologies such as flash-based SSDs remains undecided. To address this, it is important to consider PCM SSD devices not just from a device standpoint, but also from a holistic perspective.This article presents the results of our performance study of a recent all-PCM SSD prototype. The average latency for a 4KiB random read is 6.7μs, which is about 16× faster than a comparable eMLC flash SSD. The distribution of I/O response times is also much narrower than flash SSD for both reads and writes. Based on the performance measurements and real-world workload traces, we explore two typical storage use cases: tiering and caching. We report that the IOPS/$ of a tiered storage system can be improved by 12-66% and the aggregate elapsed time of a server-side caching solution can be improved by up to 35% by adding PCM.Our results show that (even at current price points) PCM storage devices show promising performance as a new component in enterprise storage systems.

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Section: Background and Related Workmentioning

confidence: 99%

Evaluating Phase Change Memory for Enterprise Storage Systems

et al. 2014

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“…Kim et al [5] proposed a page replacement algorithm for hybrid memory architecture with single chip CPU/GPU, which is logically partitioned into three regions. They reduced the number of PCM writes by first loading a GPU data to a write buffer that is allocated in DRAM and use a write-back policy.…”

Section: Related Workmentioning

confidence: 99%

“…Not surprisingly, researchers have suggested various approaches to mitigate the above weaknesses of PCM [1,3,5,7,9,10,13]. Most of the works focused on reducing the number of PCM writes that are crucially concerned with the performance of hybrid memory architecture due to asymmetric read/write latency and limited lifespan of PCM.…”

Section: Introductionmentioning

confidence: 99%

“…Although these approaches efficiently reduce the number of PCM writes, they also incur performance degradation because they should check both DRAM and PCM when the page to be referenced does not exist in DRAM write-buffer. Meanwhile, other studies proposed some page replacement algorithms for hybrid memory architecture [1,5,7,10]. To reduce the number of PCM writes, their schemes allocate pages to DRAM or PCM after classifying them into writeintensive ones and read-intensive ones.…”

Section: Introductionmentioning

confidence: 99%

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M-Clock

Kang

Kim

Eom

2015

Proceedings of the 30th Annual ACM Symposium on Applied Computing

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Phase Change Memory (PCM) has drawn great attention as a main memory due to its attractive characteristics such as non-volatility, byte-addressability, and in-place update. However, since the capacity of PCM is not fully mature yet, hybrid memory architecture that consists of DRAM and PCM has been suggested. In addition, page replacement algorithm based on hybrid memory architecture is actively being studied because existing page replacement algorithms cannot be used on hybrid memory architecture in that they do not consider the two weaknesses of PCM: high write latency and low endurance. In this paper, to mitigate the above hardware limitations of PCM, we revisit the page cache layer for the hybrid memory architecture. We also propose a novel page replacement algorithm, called M-CLOCK, to improve the performance of hybrid memory architecture and the lifespan of PCM. In particular, M-CLOCK aims to reduce the number of PCM writes that negatively affect the performance of hybrid memory architecture. Experimental results clearly show that M-CLOCK outperforms the stateof-the-art page replacement algorithms in terms of the number of PCM writes and effective memory access time by up to 98% and 34%, respectively.

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“…Hybrid memory system has shown strong potential to alleviate the power issue of GPUs. Several studies have investigated hybrid memory architecture for global memory on GPU [7,8,9,10]. Satyamoorthy has studied STT-RAM-based and MRAM-based shared memory for GPUs [11,12].…”

Section: Introductionmentioning

confidence: 99%

A STT-RAM-based low-power hybrid register file for GPGPUs

Chen

Sun

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Recently, general-purpose graphics processing units (GPGPUs) have been widely used to accelerate computing in various applications. To store the contexts of thousands of concurrent threads on a GPU, a large static random-access memory (SRAM)-based register file is employed. Due to high leakage power of SRAM, the register file consumes 20% to 40% of the total GPU power consumption. Thus, hybrid memory system, which combines SRAM and the emerging non-volatile memory (NVM), has been employed for register file design on GPUs. Although it has shown strong potential to alleviate the power issue of GPUs, existing hybrid memory solutions might not exploit the intrinsic feature of GPU register file. By leveraging the warp schedule on GPU, this paper proposes a hybrid register architecture which consists of a NVM-based register file and mixed SRAM-based write buffers with a warp-aware write back strategy. Simulation results show that our design can eliminate 64% of write accesses to NVM and reduce power of register file by 66% on average, with only 4.2% performance degradation. After we apply the power gating technique, the register power is further reduced to 25% of SRAM counterpart on average.

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Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU

Cited by 29 publications

References 9 publications

Evaluating Phase Change Memory for Enterprise Storage Systems

Evaluating Phase Change Memory for Enterprise Storage Systems

M-Clock

A STT-RAM-based low-power hybrid register file for GPGPUs

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