Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs

Yu, Lizhen; Hung, J. H.; Sheu, Boryau; Huynh, Bill; Nguyen, Loc Bao; Wu, Shianling; Wang, Laung-Terng; Wen, Xiaoqing

doi:10.1109/dft.2010.47

Cited by 3 publications

(1 citation statement)

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“…Once the BIST circuit is generated, it cannot detect more other faults. This lacks the flexibility of design debug, especially in the early phase of the design [14,15]. What's more, a design with multiple memories requires embedding multiple BIST circuits into the chip as shown in (Fig.…”

Section: Introductionmentioning

confidence: 99%

A Novel Controllable BIST Circuit for embedded SRAM

Lin¹,

Peng²,

Wang³

2016

TOEEJ

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With increasingly stringent requirements for memory test, the complexity of the test algorithm is increasing. This will make BIST (Build-In-Self-Test) circuit more complex and the area of BIST circuit larger. This paper proposes a novel controllable BIST circuit. The controllable BIST circuit provides a cost-effective solution that supports a variety of March algorithms and SRAM embedded testing operation modes. It controls the test patterns with three additional input ports. And it indicates the algorithm progress, the test result and the number of fails with three output ports. To achieve test patterns generation, analy-sis and test results recording, the proposed BIST circuit contains five internal functional modules, which are Address Gener-ator, Control Generator, Data Generator, Data Comparator and Fail Accumulator. The test patterns of the proposed BIST cir-cuit are controlled by external signals. It is not only suitable for any existing march algorithms but also leaves room for ex-tension if needed.

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Section: Introductionmentioning

confidence: 99%