Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform

Umuroglu, Yaman; Morrison, Donn; Jahre, Magnus

doi:10.1109/fpl.2015.7293939

Cited by 43 publications

(32 citation statements)

References 25 publications

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“…Source-Oriented [15,27,69,[77][78][79][80] Destination-Oriented [16,26,30,73,81] Grid [28,70,82] Heuristic [29,31,32,75,76,83,84] Source-oriented Partition. it is convenient to determine the partitions that need the updated vertex property in the graph processing.…”

Section: Partitioning Schemes Graph Acceleratorsmentioning

confidence: 99%

A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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Graph is a well known data structure to represent the associated relationships in a variety of applications, e.g., data science and machine learning. Despite a wealth of existing efforts on developing graph processing systems for improving the performance and/or energy efficiency on traditional architectures, dedicated hardware solutions, also referred to as graph processing accelerators, are essential and emerging to provide the benefits significantly beyond those pure software solutions can offer. In this paper, we conduct a systematical survey regarding the design and implementation of graph processing accelerator. Specifically, we review the relevant techniques in three core components toward a graph processing accelerator: preprocessing, parallel graph computation and runtime scheduling. We also examine the benchmarks and results in existing studies for evaluating a graph processing accelerator. Interestingly, we find that there is not an absolute winner for all three aspects in graph acceleration due to the diverse characteristics of graph processing and complexity of hardware configurations. We finially present to discuss several challenges in details, and to further explore the opportunities for the future research.

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Section: Partitioning Schemes Graph Acceleratorsmentioning

confidence: 99%

A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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“…There have also been several proposals for accelerators for specific graph applications. Both PageRank [22] and variations of breadth-first-search and single-source shortest path algorithms [6,8,17,31,33] have been implemented for FPGAs and ASICs. In addition, there are other studies that attempt to provide abstract templates for regular graph processing [12,24].…”

Section: Introductionmentioning

confidence: 99%

A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators

Ayupov

Yesil

Özdal

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Graph applications have been gaining importance in the last decade due to emerging big data analytics problems such as web graphs, social networks, and biological networks. For these applications, traditional CPU and GPU architectures suffer in terms of performance and power consumption due to irregular communications, random memory accesses, and load balancing problems. It has been shown that specialized hardware accelerators can achieve much better power and energy efficiency compared to the general purpose CPUs and GPUs. In this work, we present a template-based methodology specifically targeted for hardware accelerator design of big-data graph applications. Important architectural features that are key for energy efficient execution are implemented in a common template. The proposed template-based methodology is used to design hardware accelerators for different graph applications with little effort. Compared to an application-specific high-level synthesis (HLS) methodology, we show that the proposed methodology can generate hardware accelerators with up to 18x better energy efficiency and requires less design effort.

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“…Despite its simplicity, its parallelization has been a real challenge but it remains a good candidate for acceleration. To date, different accelerators have been targeted to improve the performance of this algorithm such as GPGPUs [11] and FPGAs [28]. The Intel Xeon Phi, also known as MIC (Intel's Many Integrated Core Architecture), is a massively parallel off-the-shelf system consisting of up to 60 cores with 4-way simultaneous multi-threading (SMT) for a maximum of 240 logical cores [21].…”

Section: Introductionmentioning

confidence: 99%

Breadth first search vectorization on the Intel Xeon Phi

Paredes

Riley

Luján

2016

Proceedings of the ACM International Conference on Computing Frontiers

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Breadth First Search (BFS) is a building block for graph algorithms and has recently been used for large scale analysis of information in a variety of applications including social networks, graph databases and web searching. Due to its importance, a number of different parallel programming models and architectures have been exploited to optimize the BFS. However, due to the irregular memory access patterns and the unstructured nature of the large graphs, its efficient parallelization is a challenge. The Xeon Phi is a massively parallel architecture available as an off-the-shelf accelerator, which includes a powerful 512 bit vector unit with optimized scatter and gather functions. Given its potential benefits, work related to graph traversing on this architecture is an active area of research.We present a set of experiments in which we explore architectural features of the Xeon Phi and how best to exploit them in a top-down BFS algorithm but the techniques can be applied to the current state-of-the-art hybrid, top-down plus bottom-up, algorithms.We focus on the exploitation of the vector unit by developing an improved highly vectorized OpenMP parallel algorithm, using vector intrinsics, and understanding the use of data alignment and prefetching. In addition, we investigate the impact of hyperthreading and thread affinity on performance, a topic that appears under researched in the literature. As a result, we achieve what we believe is the fastest published top-down BFS algorithm on the version of Xeon Phi used in our experiments. The vectorized BFS topdown source code presented in this paper can be available on request as free-to-use software.

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Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform

Cited by 43 publications

References 25 publications

A Survey on Graph Processing Accelerators: Challenges and Opportunities

A Survey on Graph Processing Accelerators: Challenges and Opportunities

A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators

Breadth first search vectorization on the Intel Xeon Phi

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