Hybrid Boolean Networks as Physically Unclonable Functions

Abstract

We introduce a Physically Unclonable Function (PUF) based on an ultra-fast chaotic network known as a Hybrid Boolean Network (HBN) implemented on a field programmable gate array. The network, consisting of N coupled asynchronous logic gates displaying dynamics on the sub-nanosecond time scale, acts as a 'digital fingerprint' by amplifying small manufacturing variations during a period of transient chaos. In contrast to other PUF designs, we use both N-bits per challenge and obtain N-bits per response by considering challenges to be initial states of the N-node network and responses to be states captured during the subsequent chaotic transient. We find that the presence of chaos amplifies the frozen-in randomness due to manufacturing differences and that the extractable entropy is approximately 50% of the maximum of N 2 N bits. We obtain PUF uniqueness and reliability metrics µ inter = 0.40±0.01 and µ intra = 0.05±0.00, respectively, for an N = 256 network. These metrics correspond to an expected Hamming distance of 102.4 bits per response. Moreover, a simple cherry-picking scheme that discards noisy bits yields µ intra < 0.01 while still retaining ∼ 200 bits/response (corresponding to a Hamming distance of ∼ 80 bits/response). In addition to characterizing the uniqueness and reliability, we demonstrate super-exponential scaling in the entropy up to N = 512 and demonstrate that PUFmeter, a recent PUF analysis tool, is unable to model our PUF. Finally, we characterize the temperature variation of the HBN-PUF and propose future improvements.

A Lightweight ECC-based Three-Factor Mutual Authentication and Key Agreement Protocol for WSNs in IoT

“…In our protocol, we use a recently proposed PUF scheme. HBN-PUF [32] is a strong, chaos-enhanced, and asynchronous PUF. According to [33], the creators of HBN-PUF aim to move quickly to commercialize this technology.…”

High-Resolution Waveform Capture Device on a Cyclone-V FPGA

“…Such measurements have important consequences for FPGA-based cryptographic primitives such as those described in Ref. [27], which rely on obfuscation of these properties. As such, the WCD may open new attacks on these security architectures.…”

“…IV, we place the RO compactly within a single MLAB and control the initial state of the RO using a multiplexer following the appendix of Ref. [27]. This yields Verilog code of the form 'ring[i] = enable ?…”

Long-Range Pulse Interactions in Unclocked FPGAs

“…T Echnologies that use unclocked or asynchronous logic designs in Field-Programmable Gate Arrays (FPGAs) to realize software-defined delays are prevalent throughout the engineering literature. Recent applications include timeto-digital converters (TDCs) [1], [2], physically unclonable functions (PUFs) [3]- [7], true random number generators (TRNGs) [8]- [11], and reservoir computers [12]- [14]. In many of these designs, cascaded logic elements (often an even number of inverters or NOT-gates [15], [16]) are used to approximate ideal delays for logic levels and switching times.…”