Hybrid approximate multiplier architectures for improved power-accuracy trade-offs

Abstract

Abstract-Approximate computing forms a promising design alternative for inherently error resilient applications, trading accuracy for power savings. In this paper, we exploit multi-level approximation, i.e. at the algorithmic, the logic and the circuit level, to design low power approximate arithmetic architectures for hardware multipliers. Motivated from the limited power savings that approximation techniques can achieve in isolation, we explore hybrid methods that apply simultaneously more than one techniques from different layers. We introduce the concept of perforation for approximate arithmetic circuit design and we explore the newly defined design space of hybrid designs showing that it leads to lower power consumption at every examined error range. To address the increased complexity of the target design space, we introduce an heuristic optimization technique and the corresponding design framework that automatically generates hybrid low-power approximate multipliers requiring a small number of design evaluations, i.e. synthesis, simulation, power and timing analysis. Through extensive experimentation, we show that the proposed techniques converge towards optimal solutions and deliver approximate designs that are always more efficient with respect to state-of-art approaches. Power savings of 11% are reported for small error bounds and more than 30% in case of more relaxed error constraints.

On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

“…Zervakis et al [41] introduced a technique for partial product perforation in the Booth encoding. It leads to a simpler partial product addition stage but also a significant decrease in the accuracy.…”

Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers

“…On the other hand, approximations on the partial product generation deliver simpler partial product arrays, and thus, there is significant reduction in the critical paths and the accumulation complexity [13]. Although vertical cross-layer approximation techniques have recently emerged [25,28] showing promising results, the full potential of horizontal, i.e., within the same level of design abstraction, and cooperative approximation techniques still remains an open issue for further exploration and exploitation. In this work, we explore for the first time, the efficiency of cooperative arithmetic-level approximate techniques targeting energy-efficient multiplier designs.…”

Design automation and synthesis techniques for approximate computing

“…Under iso-area (iso-power) conditions, increasing the error value results in a decrease in the power consumption (area complexity). The addition of this extra dimension induces an extra overhead to the already increased complexity of efficient systems design, since the design space may increase exponentially [24,41]. Moreover, the designers have to find the Pareto front points that optimize the efficiency but also guarantee that the output quality constraints are satisfied.…”

“…In hardware design, approximate computing can be applied in three distinct layers [41,58,86], i.e., the algorithmic level, e.g., omit computations [58], the logic level, e.g., truth table altering [63], and the circuit level, e.g., Voltage Over-scaling [85]. Voltage Over-Scaling (VOS) is one the most widely used techniques to generate energy efficient approximate circuits.…”

“…Voltage Over-Scaling (VOS) is one the most widely used techniques to generate energy efficient approximate circuits. VOS is applied to any circuit by keeping the operating frequency constant and decreasing the supply voltage below its nominal value [41]. The voltage decrease reduces the power consumption significantly, but erroneous outputs can be generated due to the circuit paths that fail to meet the time requirements [85].…”