Hybrid Approach for Parallelization of Sequential Code with Function Level and Block Level Parallelization

Kumar, K. Kiran; Pappu, Aasish Kumar; Kumar, K. Sarath; Sanyal, Sudip

doi:10.1109/parelec.2006.44

Cited by 3 publications

(3 citation statements)

References 6 publications

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“…Such tools are very much useful when the program flow depends predominantlyupon the user inputs. [29] …”

Section: Semiautomatic Parallelizationmentioning

confidence: 99%

A Review of Parallelization Tools and Introduction to Easypar

Sah¹,

Vaidya²

2012

IJCA

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Multicore processors have paved the way to increase the performance of any application by the virtue of benefits of parallelization. However, exploiting parallelism from a program is not easy, as it requires parallel programming expertise. In addition, manual parallelization is a cumbersome, time consuming and inefficient process. A number of tools proposed in the past ease the effort of parallel programming. This paper presents a classification of such parallelization tools. The classification is based on different eras of tool development, role playedby these tools in various parallelization stages, and features provided by parallel program assistance tools. Classification of tools concludes with a discussion on requirements of futuristic parallelization tools. Finally, this paper proposesour on-going work about the development of a parallel program assistance tool called EasyPar, which is a parallel program assistance tool.

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“…Such tools are very much useful when the program flow depends predominantlyupon the user inputs. [29] …”

Section: Semiautomatic Parallelizationmentioning

confidence: 99%

A Review of Parallelization Tools and Introduction to Easypar

Sah¹,

Vaidya²

2012

IJCA

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“…[3] presents an extended I-Test, for detecting data dependencies in complex loop regions. The fully automated function and block level based parallelizer [4] identifies dependencies within the code by variable scope analysis. [5] introduces a function level parallelizer specialised in recursive functions using compile and run-time techniques.…”

Section: Profiling-based Paralleliza-tion Of Functionsmentioning

confidence: 99%

“…In the following section [3] a detailed description of the profiling-based parallelization of functions, which is a straight-forward approach in parallelization is described. A brief overview about the formulation of architecture constraints for the design space exploration with Integer Linear Programming is given in section [4]. Section [5] presents a lightweight on-chip message passing software library for communication between tasks of the parallel program.…”

Section: Introductionmentioning

confidence: 99%

Application-driven architecture synthesis of on-chip Multiprocessor systems

Bobda

Mahr

Andres

et al. 2010

2010 International Conference on High Performance Computing &Amp; Simulation

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The exploitation of the rapid growing field of Multiprocessor on chip requires efficient design methodologies and tools. Besides the extraction of task level parallelism, architecture synthesis is of growing importance, in particular for programmable hardware devices, which allow for the reuse of the hardware across applications. Using programmable devices to implement on-chip multiprocessor systems, the architecture of the computing and communication infrastructure can be tailored to match the inherent parallelism of applications. In this paper, we present a design flow for the generation of the computing and communication architecture for a given application. The automatic extraction of the parallelism is presented first, followed by the application-driven synthesis of the computing and communication architecture. Finally, a light weight on-chip communication library as well as a tool-chain for the design of on-chip multiprocessor on programmable devices is explained. Each step of the design process is evaluated with different examples.

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