hwloc: A Generic Framework for Managing Hardware Affinities in HPC Applications

Broquedis, François; Clet-Ortega, Jérôme; Moreaud, Stéphanie; Furmento, Nathalie; Goglin, Brice; Mercier, Guillaume; Thibault, Samuel; Namyst, Raymond

doi:10.1109/pdp.2010.67

Cited by 299 publications

(209 citation statements)

References 13 publications

Supporting

Mentioning

197

Contrasting

Unclassified

Order By: Relevance

“…We reused the hwloc library [2] to obtain the topology of the underlying computation node. Once discovered, the runtime decides how to decompose the hardware resources (processing elements, caches, etc.)…”

Section: Methodsmentioning

confidence: 99%

An Implementation of the Codelet Model

Suettlerlein

Zuckerman

Gao

2013

Euro-Par 2013 Parallel Processing

View full text Add to dashboard Cite

Abstract. Chip architectures are shifting from few, faster, functionally heavy cores to abundant, slower, simpler cores to address pressing physical limitations such as energy consumption and heat expenditure. As architectural trends continue to fluctuate, we propose a novel program execution model, the Codelet model, which is designed for new systems tasked with efficiently managing varying resources. The Codelet model is a fine-grained dataflow inspired model extended to address the cumbersome resources available in new architectures. In the following, we define the Codelet execution model as well as provide an implementation named DARTS. Utilizing DARTS and two predominant kernels, matrix multiplication and the Graph 500's breadth first search, we explore the validity of fine-grain execution as a promising and viable execution model for future and current architectures. We show that our runtime is on par or performs better than AMD's highly-optimized parallel library for matrix multication, outperforming it on average by 1.40× with a speedup up to 4×. Our implementation of the parallel BFS outperforms Graph 500's reference implementation (with or without dynamic scheduling) on average by 1.50× with a speed up of up to 2.38×.

show abstract

Section: Methodsmentioning

confidence: 99%

An Implementation of the Codelet Model

Suettlerlein

Zuckerman

Gao

2013

Euro-Par 2013 Parallel Processing

View full text Add to dashboard Cite

show abstract

“…If we also know the node's hardware topology, we can associate a memory sample with a specific portion of it. Tools such as hwloc [5] and likwid [6] exist to detect the available hardware topology on a system. We use a modification of likwid suited to integrate with our existing codebase.…”

Section: A Node Hardware Topologymentioning

confidence: 99%

Dissecting On-Node Memory Access Performance: A Semantic Approach

Giménez

Gamblin

Rountree

et al. 2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

View full text Add to dashboard Cite

Abstract-Optimizing memory access is critical for performance and power efficiency. CPU manufacturers have developed sampling-based performance measurement units (PMUs) that report precise costs of memory accesses at specific addresses. However, this data is too low-level to be meaningfully interpreted and contains an excessive amount of irrelevant or uninteresting information.We have developed a method to gather fine-grained memory access performance data for specific data objects and regions of code with low overhead and attribute semantic information to the sampled memory accesses. This information provides the context necessary to more effectively interpret the data. We have developed a tool that performs this sampling and attribution and used the tool to discover and diagnose performance problems in real-world applications. Our techniques provide useful insight into the memory behavior of applications and allow programmers to understand the performance ramifications of key design decisions: domain decomposition, multi-threading, and data motion within distributed memory systems.

show abstract

“…It is also completely transparent: applications cannot determine whether they are running under CPU speed degradation unless they read the inria-00535534, version 2 -14 Jul 2011 Figure 1: Architecture of a dual Intel L5420 machine, as shown by hwloc [6]. Cores sharing their L2 cache cannot change speed independently.…”

Section: Related Workmentioning

confidence: 99%

Methods for Emulation of Multi-core CPU Performance

Buchert

Nussbaum

Gustedt

2011

2011 IEEE International Conference on High Performance Computing and Communications

View full text Add to dashboard Cite

Abstract-When validating or evaluating real distributed applications, it is useful to be able to test the application in a large range of environments. In that context, emulation of CPU performance enables researchers to investigate how the performance of the application is affected by the performance of the participating CPUs. Using a homogeneous cluster of fast multi-core nodes, it is therefore possible to evaluate how an application would behave on a heterogeneous set of nodes, with varying performance and number of cores.In this paper, three new methods for the emulation of CPU performance in the multi-core case are proposed: Fracas, CPUGov, and CPU-Hogs. Fracas relies on smart configuration of the Linux scheduler to achieve the desired emulation, CPUGov leverages the hardware CPU frequency scaling, and CPUHogs is a multi-core implementation of a CPU burner. These methods are compared and evaluated together with existing methods, with a set of micro-benchmarks, and show significant improvements over state-of-the-art solutions.

show abstract

hwloc: A Generic Framework for Managing Hardware Affinities in HPC Applications

Cited by 299 publications

References 13 publications

An Implementation of the Codelet Model

An Implementation of the Codelet Model

Dissecting On-Node Memory Access Performance: A Semantic Approach

Methods for Emulation of Multi-core CPU Performance

Contact Info

Product

Resources

About