HW/SW-database-codesign for compressed bitmap index processing

Haas, Sebastian; Karnagel, Tomas; Arnold, Oliver; Laux, Erik; Schlegel, Benjamin; Fettweis, Gerhard; Lehner, Wolfgang

doi:10.1109/asap.2016.7760772

Cited by 3 publications

(3 citation statements)

References 14 publications

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“…They have regarded the locality and ILP metrics to indicate performance. The locality includes LRU stack models, Independent reference models, density functions (temporal and spatial), set models, and memory reuse distance models [51]- [54].…”

Section: Workload Characterizationmentioning

confidence: 99%

Dependency Prediction of Long-Time Resource Uses in HPC Environment

Upadhyay,

Singh,

Dwivedi

2023

IEEE Access

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High-Performance computing provides a new infrastructure for scientific calculation and its simulation. However, unbalanced load distribution among the processors causes a decreased performance in such computations, and creates a massive requirement of computing resource allocation, that requires an increased simulation. Therefore long-range resource utilization prediction becomes essential to achieve optimal performance in an HPC environment. This paper introduces a novel ensemble technique, which includes two algorithms, the Feature-based capability prediction algorithm(FBCA), and the Accuracy and Relative Runtime Error Prediction Algorithm (ARRE). A three-level architectural framework (the simulation environment, resource prediction, and resource queue) has also been proposed and tested on Phold and SoS. The proposed framework can deal with the requirements of computing and simulations. The FBCA algorithm reduces the redundancy between available features, and the ARRE algorithm ensures our ensemble technique's effectiveness. We have compared the performance of the proposed schemes with other existing methods such as the Regressive Approach, Linear Regression and Random Forest, and found that our proposed algorithm achieves better accuracy from 8% to 18%.

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Section: Workload Characterizationmentioning

confidence: 99%

Dependency Prediction of Long-Time Resource Uses in HPC Environment

Upadhyay,

Singh,

Dwivedi

2023

IEEE Access

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“…The energy consumption reductions with the Tensilica LX5 with FLIX TIE were due to the high energy-efficiency of computations with application-specific configurable hardware. Pre-configured fixed instruction set processors generally consume much more energy than specialized hardware [31][32][33]. This case study quantified this energy consumption reduction to be over three orders of magnitude for the RLNC encoding and decoding.…”

Section: Energy Consumptionmentioning

confidence: 99%

“…A general strategy for boosting computing performance while lowering energy consumption is to employ an application-specific instruction-set processor (ASIP) instead of a general-purpose fixed instruction-set processor. The ASIP approach typically achieves speedups of up to three orders of magnitude, while reducing power consumption to a fraction of a standard fixed instruction-set processor, such as a reduced instruction set computer (RISC) processor [31][32][33]. While the computing aspects of RLNC encoding and decoding on fixed instruction-set processors have been extensively studied, to the best of our knowledge, the RLNC encoding and decoding performance on ASIP systems has not previously been examined in detail.…”

Section: Introductionmentioning

confidence: 99%

Hardware Acceleration for RLNC: A Case Study Based on the Xtensa Processor with the Tensilica Instruction-Set Extension

et al. 2018

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Random linear network coding (RLNC) can greatly aid data transmission in lossy wireless networks. However, RLNC requires computationally complex matrix multiplications and inversions in finite fields (Galois fields). These computations are highly demanding for energy-constrained mobile devices. The presented case study evaluates hardware acceleration strategies for RLNC in the context of the Tensilica Xtensa LX5 processor with the tensilica instruction set extension (TIE). More specifically, we develop TIEs for multiply-accumulate (MAC) operations for accelerating matrix multiplications in Galois fields, single instruction multiple data (SIMD) instructions operating on consecutive memory locations, as well as the flexible-length instruction extension (FLIX). We evaluate the number of clock cycles required for RLNC encoding and decoding without and with the MAC, SIMD, and FLIX acceleration strategies. We also evaluate the RLNC encoding and decoding throughput and energy consumption for a range of RLNC generation and code word sizes. We find that for GF ( 2 8 ) and GF ( 2 16 ) RLNC encoding, the SIMD and FLIX acceleration strategies achieve speedups of approximately four hundred fold compared to a benchmark C code implementation without TIE. We also find that the unicore Xtensa LX5 with SIMD has seven to thirty times higher RLNC encoding and decoding throughput than the state-of-the-art ODROID XU3 system-on-a-chip (SoC) operating with a single core; the Xtensa LX5 with FLIX, in turn, increases the throughput by roughly 25% compared to utilizing only SIMD. Furthermore, the Xtensa LX5 with FLIX consumes roughly four orders of magnitude less energy than the ODROID XU3 SoC.

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Parallel acceleration of CPU and GPU range queries over large data sets

et al. 2020

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Data management systems commonly use bitmap indices to increase the efficiency of querying scientific data. Bitmaps are usually highly compressible and can be queried directly using fast hardware-supported bitwise logical operations. The processing of bitmap queries is inherently parallel in structure, which suggests they could benefit from concurrent computer systems. In particular, bitmap-range queries offer a highly parallel computational problem, and the hardware features of graphics processing units (GPUs) offer an alluring platform for accelerating their execution.In this paper, we present four GPU algorithms and two CPU-based algorithms for the parallel execution of bitmap-range queries. We show that in 98.8% of our tests, using real and synthetic data, the GPU algorithms greatly outperform the parallel CPU algorithms. For these tests, the GPU algorithms provide up to 54.1 × speedup and an average speedup of 11.5× over the parallel CPU algorithms. In addition to enhancing performance, augmenting traditional bitmap query systems with GPUs to offload bitmap query processing allows the CPU to process other requests.

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HW/SW-database-codesign for compressed bitmap index processing

Cited by 3 publications

References 14 publications

Dependency Prediction of Long-Time Resource Uses in HPC Environment

Dependency Prediction of Long-Time Resource Uses in HPC Environment

Hardware Acceleration for RLNC: A Case Study Based on the Xtensa Processor with the Tensilica Instruction-Set Extension

Parallel acceleration of CPU and GPU range queries over large data sets

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