HW/SW architecture for speech recognition acceleration

Abstract

This paper describes a new hardware architecture for fast Acoustic Model scoring in embedded speech recognition systems by integrating an 8-way data-path with a NOR Flash array. This architecture localizes computation of critical algorithms and reduces decode latency and CPU load by 50% for large acoustic models, resulting in lower word error rates for natural language speech recognition.

Speech Control System for Robot Based on Raspberry Pi

“…CMU (Carnegie Mellon University) Sphinx Serials [3] is another popular recognition engine which has 4 generations. The 1 st Sphinx is developed by Kai-Fu Lee and his partners.…”