“…Beckmann et al [113] envisioned a combination of a P4-capable ASIC with a DRAM scale match-action table. A packet firstly is preconstructed the match key field in ASIC, and sent to a FPGA which stores network states in DRAM.…”
“…Beckmann et al [113] envisioned a combination of a P4-capable ASIC with a DRAM scale match-action table. A packet firstly is preconstructed the match key field in ASIC, and sent to a FPGA which stores network states in DRAM.…”
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