HPS, a new microarchitecture: rationale and introduction

Patt, Yale N.; Hwu, Wen mei; Shebanow, Michael

doi:10.1145/18906.18916

Cited by 53 publications

(19 citation statements)

References 6 publications

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“…Traditional out-of-order pipelines provide programmers with a sequential interface, yet internally execute instructions in parallel, based on dynamic analysis of data dependencies [16]. This section, therefore, discusses how dynamic dependency analysis can be extended to operate at the task-level.…”

Section: Tasks As Abstract Instructionsmentioning

confidence: 99%

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A Dynamically Adaptable Hardware Transactional Memory

Lupon

Magklis

González

2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-We present Task Superscalar, an abstraction of instruction-level out-of-order pipeline that operates at the tasklevel. Like ILP pipelines, which uncover parallelism in a sequential instruction stream, task superscalar uncovers tasklevel parallelism among tasks generated by a sequential thread. Utilizing intuitive programmer annotations of task inputs and outputs, the task superscalar pipeline dynamically detects intertask data dependencies, identifies task-level parallelism, and executes tasks out-of-order.Furthermore, we propose a design for a distributed task superscalar pipeline frontend, that can be embedded into any manycore fabric, and manages cores as functional units.We show that our proposed mechanism is capable of driving hundreds of cores simultaneously with non-speculative tasks, which allows our pipeline to sustain work windows consisting of tens of thousands of tasks. We further show that our pipeline can maintain a decode rate faster than 60ns per task and dynamically uncover data dependencies among as many as ∼50,000 in-flight tasks, using 7MB of on-chip eDRAM storage. This configuration achieves speedups of 95-255x (average 183x) over sequential execution for nine scientific benchmarks, running on a simulated CMP with 256 cores.Task superscalar thus enables programmers to exploit manycore systems effectively, while simultaneously simplifying their programming model.

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Section: Tasks As Abstract Instructionsmentioning

confidence: 99%

“…Perhaps most common among ILP designs, are dynamicallyscheduled out-of-order processors, which maintain a window of pending instructions, and dynamically schedule them in a dataflow manner [16].…”

Section: Related Workmentioning

confidence: 99%

A Dynamically Adaptable Hardware Transactional Memory

Lupon

Magklis

González

2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

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“…The hardware required to support speculative execution is very similar to the hardware required to support out-of-order execution [21]- [23], [44], [54], [58]. The role of this hard-ware is to maintain the external appearance of the sequential semantics of the program.…”

Section: ) Superscalar Executionmentioning

confidence: 99%

Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling

Moshovos¹,

Sohi

2001

Proc. IEEE

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“…Therefore, superscalar and VLIW (very large instruction word) machines have been designed, which can execute several instructions in parallel. In order to use these resources the instructions are reordered by the hardware Tho64,Tom67,PHS85,Soh90] or by compiler techniques like basic block instruction scheduling LDSM80, HG83, GM86, EK92], trace scheduling Fis81,Ell85] and software pipelining RG81,Lam88,Rau94]. To ensure correctness, the order between dependent instructions must be maintained, which restricts reordering and parallelism.…”

Section: Introductionmentioning

confidence: 99%

Removing anti dependences by repairing

Ertl

Krall

1996

Lecture Notes in Computer Science

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Abstract. Anti dependences (write-after-read dependences) constrain the reordering of instructions and limit the e ectiveness of instruction scheduling and software pipelining techniques for superscalar and VLIW processors. Repairing solves this problem: If the de nition of a variable is moved before a previous use of that variable, compiler-generated repair code reconstructs the value that the de nition destroyed. Repairing features several potential advantages over register renaming, another technique for removing anti dependences: less register pressure, less loop unrolling and fewer move instructions.

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HPS, a new microarchitecture: rationale and introduction

Cited by 53 publications

References 6 publications

A Dynamically Adaptable Hardware Transactional Memory

A Dynamically Adaptable Hardware Transactional Memory

Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling

Removing anti dependences by repairing

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