HPDP: Architecture and design flow: High performance data processor

Dokianaki, Olga; Baumgarte, V.; Syed, Mohsin; Papadas, C.; Helfers, T.; Dramitinos, George; Scholastique, Thierry; Kogan, Michael D.; Saenger, Ingo; Lacan, Stefan; Markakis, Onoufrios; Hili, Laurent

doi:10.1109/ahs.2017.8046360

Cited by 2 publications

(1 citation statement)

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“…This hinders their possible application in constrained environments (space in particular, but also industrial, autonomous vehicles, flying drones, high energy physics), where their radiation tolerance features have been exhaustively investigated (especially for Google and Myriad 2 devices) by ESA and NASA [26], [27] to quantify Single-Event Error (SEE) parameters like Single-Event Latch-up (SEL), Single-Event Upset (SEU) and Single-Event Functional Interrupt (SEFI). A custom solution that was specifically developed for the space sector is represented by the H2020-funded project Hi-SIDE, which has delivered a payload unit based on the High-Performance Data Processor (HPDP) [28]- [30], implemented on the STMicroelectronics 65 nm radiation-hardened technology. It is composed of two scalar Microprocessor without Interlocked Pipelined Stages (MIPS) and a 5x8 2D array of 16-bit Arithmetic Logic Units (ALUs) connected in a systolic fashion.…”

Section: B Cots Devicesmentioning

confidence: 99%

Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications

Monopoli,

Zulberti,

Nannipieri

et al. 2023

2023 European Data Handling &Amp; Data Processing Conference (EDHPC)

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Intelligence has gained widespread adoption across different industrial sectors, serving as a versatile tool to carry out a diverse array of tasks, ranging from image classification and traffic forecasting to natural language processing and speech recognition. In the space domain, however, a special focus must be placed on area overhead, power consumption, and fault-tolerant solutions. In this particular scenario, soft General-Purpose Computing on Graphic Processing Units has the potential to revolutionise space-related activities. Indeed, by leveraging both Field Programmable Gate Array technology and Graphic Processing Unit computing, it becomes feasible to achieve highperformance capabilities without compromising neither power consumption nor radiation tolerance features. Moreover, the use of reconfigurable hardware can facilitate the acceleration of a wide range of Machine Learning algorithms, avoiding the drawbacks of excessive specialisation. This paper explores the State-of-the-Art in terms of hardware platforms for on-the-edge acceleration of Artificial Intelligence algorithms and compares it with a possible System-on-Chip implementation based on a soft-Graphic Processing Unit. Then, the attention is shifted towards the investigation of key aspects for future space missions, such as reliability and Dynamic Partial Reconfiguration. We point out the lack of European technological solutions, emphasising the promising potential offered by NanoXplore devices. We also discuss the importance of fault detection and mitigation techniques in space applications, covering the most commonly employed hardware methods for reliability enhancement and highlighting the lack of work in the field of General-Purpose Computing for Graphic Processing Units, especially in the space sector. Furthermore, we briefly examine the implementation of Dynamic Partial Reconfiguration over a System-on-Chip featuring a soft-Graphic Processing Unit IP. Finally, in the last section of the paper, we hint at future development of the project and conclude the work.

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Section: B Cots Devicesmentioning

confidence: 99%