How to Synchronize a Pausible Clock to a Reference

Synchronizer-Free Digital Link Controller

“…(i) Pausible clocking overcomes synchronization issues by halting the clock until metastability is resolved [3]; e.g., the design in [4] guarantees no glitches on stopping and starting. Metastability inside the control loop may lead to an arbitrary delay of the final pulse on stopping.…”

“…We use the receiver's clock to sample whether the sender's address pointer is currently by more or less than N/2 cells ahead of the receiver's address pointer. 4 . This occurs at each time t when = p r (t) mod N = c r (t) mod N, which means that if the buffer is exactly half full, we had that p s (t) mod N = + N/2 mod N, i.e., the sender accesses cell + N/2 mod N at precisely the same time.…”

“…Hence, the most recent access to cell was by the reader (again using also (2)), which also completed its access (as N ≥ 2 4 It is worth noting that one could use a purely combinational controller to achieve the same result, i.e., there is no need to rely on clocking. Making use of the clock does also not guarantee that stable values are sampled.…”

“…We use the receiver's clock to sample whether the sender's address pointer is currently by more or less than N/2 cells ahead of the receiver's address pointer. 4 This is where the full/empty flags come in handy. Instead of having to communicate and sample c s (t), the receiver simply samples the flag of cell + N/2 mod N when accessing cell ∈ [N ].…”

“…Previous digital controller designs resort to different methods to deal with metastability: clock-masking [2], clockpausing [3], [4], or adding synchronizers (while sacrificing latency) to maintain a realistic (yet finite) mean time between failures (MTBF) of the link [2], [5]- [8]. Downsides of these approaches are that synchronized fill level flags are inherently "stale" by the time they affect the system.…”