How accurately can we model timing in a placement engine?

Abstract

This paper presents a novel placement algorithm for timing optimization based on a new and powerful concept, which we term differential timing analysis. Recognizing that accurate optimization requires timing information from a signoff static timing analyzer, we propose an incremental placement algorithm that uses timing information from a signoff static timing engine. We propose a set of differential timing analysis equations that accurately capture the effect of placement perturbations on changes in timing from the signoff timer. We have fotmutated an incremental placement optimization problem based on differential timing analysis as a single linear programming (LP) problem which is solved to generate thc new timing-optimized placement.Our experiments show that the worst negative slack (WNS) improves by an average of 30% and the total negative slack (TNS) improves by 33% on average for a set of circuits from a 3.0 GHz microprocessor that were already synthesized and placed by a leading industrial physical synthesis tool. We also show that multiple iterations of our engine give further TNS improvements an average improvement of 5 1 %, which implies that our placer will significantly speed up timing convergence.

Pyramids: An efficient computational geometry-based approach for timing-driven placement

“…The delay on an optimally buffered long net is approximately linearly proportional to its length [11,12]. The traditional approach for timing optimization is to use a linear delay model for gates to calculate the circuit delay [4,5,6,7,8]. Static timing analysis is used to create linear programs that model the timing objective and a linear programming solver is used to generate an optimal location for each cell.…”

“…Timing-driven global placement commonly uses netweighting and net-constraints based methods to address timing [1,2,3], but they are again inadequate to solve the problem completely. Thus there is a body of work mostly using mathematical programming to incrementally improve circuit timing [4,5,6,7,8]. Mathematical programming based approaches can be expensive to solve.…”

On-Line Adjustable Buffering for Runtime Power Reduction

“…Detailed placement is a refinement step which performs small-range perturbations to generate a new optimized placement. Several approaches to detailed placement have been proposed with most focusing on wirelength minimization (e.g., [6]) or timing [5]. Our approach, to the best of our knowledge, is the first to consider the impact of detailed placement on poly gate pitch to reduce leakage which is strongly and systematically dependent on pitch.…”

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm

“…Their formulation's objective is to maximize the improvement in total negative slack of timing end points. The authors of both approaches conclude that the addition of buffering would improve their techniques [6], [24]. When these transformations are applied at the same point in a physical synthesis flow that we propose, they will be restricted by previous optimizations.…”

“…The authors of [24] propose a linear programming formulation that minimizes downstream delay to choose locations for gates in field-programmable gate arrays (FPGAs). The authors of [6] model static timing analysis (STA) in a linear programming formulation by approximating the quadratic delay of nets with a piecewise-linear function. Their formulation's objective is to maximize the improvement in total negative slack of timing end points.…”