Hotl

Xiang, Xiaoya; Ding, Chen; Luo, Hao; Bao, Bin

doi:10.1145/2490301.2451153

Cited by 14 publications

(2 citation statements)

References 46 publications

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“…These overheads are also still lower than existing simulator and binary instrumentation‐based tools. One open‐source binary instrumentation‐based tool that we tested is local, 31,32 whose runtime overhead is 49

\times

and memory overhead is 40

\times

.…”

Section: Discussionmentioning

confidence: 99%

Precise event sampling‐based data locality tools for AMD multicore architectures

Sasongko

Chabbi²,

Unat

2023

Concurrency and Computation

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SummaryWe propose ComDetective, an inter‐thread communication analyzer, and ReuseTracker, a reuse distance analyzer, that leverage the hardware features in AMD processors to support low‐overhead profiling. Both tools employ the instruction‐based sampling (IBS) facility and debug registers in AMD processors to detect inter‐thread communication and data reuse. Different from prior arts, ComDetective differentiates the communication into true and false sharing, and ReuseTracker measures reuse distance in private and shared caches by also considering cache line invalidation with low overhead. Both tools can attribute the communications and reuses to source code lines. To our knowledge these tools are two of the few profiling tools designed specifically for AMD x86 architectures using IBS. Our tools are timely and relevant considering the rise in numbers of AMD processor based data centers and HPC systems. We perform experiments to evaluate the accuracy and overheads of the proposed tools on an AMD machine with two‐socket EPYC 7352 processors. ComDetective exhibits high accuracy while introducing 5.14 runtime and 1.4 memory overheads. ReuseTracker also displays high accuracy, which is 95%, with 11.76 runtime and 1.46 memory overheads. These overheads are much lower than the overheads of existing simulators and code instrumentation‐based tools. Lastly, we demonstrate the usage of the tools by having ComDetective and ReuseTracker facilitate the code refactoring of two data mining benchmarks to improve their performance by up to 29%.

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\times

and memory overhead is 40

\times

.…”

Section: Discussionmentioning

confidence: 99%

Precise event sampling‐based data locality tools for AMD multicore architectures

Sasongko

Chabbi²,

Unat

2023

Concurrency and Computation

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“…The idea behind the success of cache memory is locality of reference in a program [8]- [11]. Program execution usually favours portion of the main memory within a short duration of time.…”

Section: Introductionmentioning

confidence: 99%

Modeling cache performance for embedded systems

et al. 2021

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This paper presents a cache performance model for embedded systems. The need for efficient cache design in embedded systems has led to the exploration of various methods of design for optimal cache configurations for embedded processor. Better users’ experiences are realized by improving performance parameters of embedded systems. This work presents a cache hit rate estimation model for embedded systems that can be used to explore optimal cache configurations using Bourneli’s binomial cumulative probability based on application of reuse distance profiles. The model presented was evaluated using three mibench benchmarks which are bitcount, basicmath and FFT for 4kb, 8kb, 16kb, 32kb and 64kb sizes of cache under 2-way, 4-ways, 8-ways and 16-ways set associative configurations, all using least recently-used (LRU) replacement policy. The results were compared with the results obtained using sim-cheetah from simplescalar simulators suite. The mean errors for bitcount, basicmath, and FFT benchmarks are 0.0263%, 2.4476%, and 1.9000% respectively. Therefore, the mean error for the three benchmarks is equal to 1.4579%. The margin of errors in the results was below 5% and within the acceptable limits showing that the model can be used to estimate hit rates of cache and to explore cache design options.

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A Fast Joint Application-Architecture Exploration Platform for Heterogeneous Systems

Maeda

Yang

et al. 2019

Embedded, Cyber-Physical, and IoT Systems

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Hotl

Cited by 14 publications

References 46 publications

Precise event sampling‐based data locality tools for AMD multicore architectures

Precise event sampling‐based data locality tools for AMD multicore architectures

Modeling cache performance for embedded systems

A Fast Joint Application-Architecture Exploration Platform for Heterogeneous Systems

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