Hot-electron-induced MOSFET degradation—Model, monitor, and improvement

Hu, Chenming; Tam, Simon; Hsu, Fu-Chieh; Ko, P.K.; Chan, T.Y.; Terrill, K.W.

doi:10.1109/t-ed.1985.21952

Cited by 920 publications

(81 citation statements)

References 35 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The substrate current is a measure of impact ionization, which itself is indicative of the channel hot carrier energy. 16,17 Clearly, the channel carrier energy increases with increasing jV D j, while the channel carriers remain "cold" in the BTI regime (jV…”

Section: Methodsmentioning

confidence: 99%

Mapping of CMOS FET degradation in bias space—Application to dram peripheral devices

Kaczer

Franco

Tyaginov

et al. 2016

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

View full text Add to dashboard Cite

Mapping and visualization of all degradation modes in both n-and p-channel field effect transistors, specifically devices for dynamic random access memory periphery, is performed in the (V G , V D) bias space applicable for complementary metal-oxide-semiconductor operation. This "all-in-one" approach allows for tracking and studying in parallel all degradation regimes, including bias temperature instability, hot carrier degradation, and off-state stress, as well as the transitions between them. It should prove beneficial when developing new very large-scale integrated technologies, since it allows for simultaneous comparison and checking of all degradation regimes and promptly identifying "weak spots" of each technology option. It also allows to choose the correct criteria (voltages or fields) at a later time and postprocessing the data as necessary.

show abstract

Section: Methodsmentioning

confidence: 99%

Mapping of CMOS FET degradation in bias space—Application to dram peripheral devices

Kaczer

Franco

Tyaginov

et al. 2016

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

View full text Add to dashboard Cite

show abstract

“…When a chip is operated for a long period of time, some of the electrons which flow in the channel of the unit transistor become trapped at the gate insulator, or break the interface between the channel and the gate insulator 27,28 , as shown in the inset of Fig. 4(a).…”

Section: Resultsmentioning

confidence: 99%

On-Chip Curing by Microwave for Long Term Usage of Electronic Devices in Harsh Environments

Park

Kim

Bae

et al. 2018

Sci Rep

View full text Add to dashboard Cite

Microwave-induced thermal curing is demonstrated to improve the reliability and to prolong the lifetime of chips containing nanoscale electron devices. A film containing graphite powder with high microwave absorbing efficiency was fabricated at low cost. The film is flexible, bendable, foldable, and attachable to a chip. A commercial off-the-shelf chip and a representative 3-dimensional (3D) metal-oxide-semiconductor field-effect transistor (MOSFET), known as FinFET, were utilized to verify the curing behaviors of the microwave-induced heat treatment. The heat effectively cured not only total ionizing dose (TID) damage from the external environment, but also internal electrical stress such as hot-carrier injection (HCI), which are representative sources of damages in MOSFET insulators. Then, the characteristics of the pre- and post-curing electron devices are investigated using electrical measurements and numerical simulations.

show abstract

“…when ÁN it is caused by electron injection as seen in most low-voltage CMOS devices. 12,13) According to the results in Figs. 13 and 14, ÁN it for the device stressed under V g ¼ 6 V is caused by hole injection.…”

Section: Resultsmentioning

confidence: 99%

Multiwave lasing in an electron-beam-pumped Ar–Xe mixture

Derzhiev¹,

Zhidkov²,

Sereda³

et al. 1990

Sov. J. Quantum Electron.

View full text Add to dashboard Cite

The phenomenon and mechanism of hot-carrier-induced on-resistance (R on ) degradation for the n-type lateral diffused metaloxide-semiconductor (MOS) transistors stressed under various gate voltages (V g ) are investigated. R on degradation of the device is found to be attributed to the interface state (N it ) generation in the N À drift region. Moreover, R on degradation is almost identical for the devices stressed under medium V g and high V g , despite the fact that bulk current of the device is much greater at high V g bias. Such an anomalous R on degradation is suggested to be the result of two combined factors: the magnitude of impact ionization rate and N it generation efficiency.

show abstract

Hot-electron-induced MOSFET degradation—Model, monitor, and improvement

Cited by 920 publications

References 35 publications

Mapping of CMOS FET degradation in bias space—Application to dram peripheral devices

Mapping of CMOS FET degradation in bias space—Application to dram peripheral devices

On-Chip Curing by Microwave for Long Term Usage of Electronic Devices in Harsh Environments

Multiwave lasing in an electron-beam-pumped Ar–Xe mixture

Contact Info

Product

Resources

About