Horizontal HALL devices: A lumped-circuit model for EDA simulators

Dimitropoulos, P.D.; Drljaca, P.M.; Popović, R.S.; Chatzinikolaou, P.

doi:10.1016/j.sna.2007.11.030

Cited by 25 publications

(11 citation statements)

References 35 publications

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“…When compared to the other existing models, the lumpedcircuit model in [9] and the accurate 8-resistance model in [10] have advantages in accuracy and take most related effects into account. While our model not only carry forward the advantages, but also ensure 90° symmetry of the model and improve AC performance.…”

Section: Verificationmentioning

confidence: 99%

“…However, several early circuit models cannot take fully into account nonlinearity, temperature drift, frequency-response and geometrical effect [6,7]. Later, a lumped-circuit model was proposed containing series of elementary cells, each cell constituted by a set of current sources and JFETs [9]. Accuracy can be improved by increasing number of elementary cells at the expense of simplicity and efficiency.…”

Section: Introductionmentioning

confidence: 99%

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A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs

Lyu

Zhu

et al. 2014

2014 International Symposium on Integrated Circuits (ISIC)

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We propose a more accurate model for CMOS Hall cross with resistors and JFETs. This model not only completely takes into account the physical effects, such as geometrical effects, temperature effects, parasitical effects, and so on, but also assures the symmetry of the model. And it consists of eight nonlinear resistors, four JFETs, four current-controlled voltage sources, and four reversed-biased diodes modeled by capacitors and constant-current sources. The model has been written in Verilog-A hardware description language and applied in Cadence Spectre simulator successfully. The simulation results of the model are in good agreement with the experimental results.

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Section: Verificationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs

Lyu

Zhu

et al. 2014

2014 International Symposium on Integrated Circuits (ISIC)

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“…The sensor is divided in elementary cells, modeled themselves with a network of standard electronic devices (resistors, current and voltage sources…). The approach, initially developed for HHDs [7], has been widened to VHDs with interesting results [8]. Nevertheless, little information is given on the number of cells required to obtain accurate results.…”

Section: Introductionmentioning

confidence: 99%

An improved compact model of the electrical behaviour of the 5-contact vertical hall-effect device

Madec

Schell

Kammerer

et al. 2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

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The goal of this work is the improvement of an existing design-oriented model of the 5-contact vertical Halleffect sensor integrated in CMOS technology. Such a model should facilitate the work of designers, permitting them to simulate the sensor, the biasing and processing electronics together with the same electrical simulator. In this paper, focus is put on two physical effects that alter the electrical behavior of the sensor: the carrier velocity saturation under high electric field, and the limitation of the current lines depth into a deep sensor. The model has been achieved with a subtle mix of theoretical considerations, numerical simulations performed with COMSOL Multiphysics  and experimental data. It has been compared with experimental data gathered from two devices, one fabricated in a low-voltage (LV) standard technology and another one in a high-voltage (HV) technology. Simulations obtained with the compact model fit the actual behavior of the LV-sensor with a root mean square error of 0.35%, and 0.8% for the HV-VHD.I.

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“…Moreover, the model depends on the device biasing method, which is a strong limitation. In another work, Dimitropoulos suggested a mixed approach consisting in dividing the VHD into sub-cells, each cell being modeled through standard electronic devices (resistors, current and voltage sources …) [7]. Nevertheless, the complexity of the model increases dramatically with the number of sub-cells, and it seems to be difficult to have an accurate and fast-simulating model with such an approach.…”

Section: Introductionmentioning

confidence: 99%

Compact modeling of vertical hall-effect devices: Electrical behavior

Madec

Schell

Kammerer

et al. 2012

10th IEEE International NEWCAS Conference

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The topic of this work is the building of a designoriented compact model of vertical Hall-effect sensors integrated in CMOS technologies. The use of such a model should facilitate the work of integrated sensors designers, permitting them to simulate the sensor, the biasing and processing electronics together with the same electrical simulator. In this paper, focus is made on the electrical behavior, i.e. the resistive behavior of a 5-contact sensor. The model is based both on theoretical considerations and on numerical simulations performed with COMSOL ® . The result is a new compact model, written in Verilog-A, with 7 input terminals and 16 parameters, mainly the sensor geometry and the technology characteristics. These parameters can be easily extracted from measurements carried out on a single sensor. Our approach is validated by FEM simulations: the results obtained with the compact model exhibit an average error lower than 1% in comparison with simulations.

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Horizontal HALL devices: A lumped-circuit model for EDA simulators

Cited by 25 publications

References 35 publications

A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs

A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs

An improved compact model of the electrical behaviour of the 5-contact vertical hall-effect device

Compact modeling of vertical hall-effect devices: Electrical behavior

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