HML, a novel hardware description language and its translation to VHDL

Li, Yanbing; Leeser, Miriam

doi:10.1109/92.820756

Cited by 43 publications

(2 citation statements)

References 11 publications

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“…An extensive overview of tools languages targeting higher abstraction levels is given in [3]. High-level languages, such as Bluespec [27], Chisel [28], OpenCL [29], HML [30] and synthesis tools [31] aim to increase design efficiency, especially in the development of hardware algorithm accelerators; however, to effectively use the high-level tools, a good understanding of RTL circuit models is required. RTL languages and models provide the developer with full control over the hardware structure, and enable the optimization of the gate-level technology.…”

Section: Hardware Description Learning Tools Existing Digital Design ...mentioning

confidence: 99%

SHDL—A Hardware Description Language and Open-Source Web Tool for Online Digital Systems Design Teaching

2023

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Hardware description languages and tools require a considerable amount of teaching activities in a digital systems design course, which is difficult to accommodate in a limited time frame, and to use for e-learning. This paper presents our user-friendly and open-source web-based digital design tool, SHDL, which is used to describe and simulate hardware components and translate them into a standard language. SHDL is a teaching language and tool for digital design, which aims to improve the teaching and learning experience in digital systems design courses. The use and evaluation of the proposed online teaching model for the Digital Electronic Systems Design (DESD) course, using the SHDL tool for e-learning during the COVID-19 phase, is presented. Using the SHDL language and web tool, we have created many examples of digital circuits that prepare students to explore their own designs. The example components can also be used as digital system modules, leading to better modularity of the final project. The use of SHDL in the DESD course has shown that the proposed language leads to fewer syntax, simulation and synthesis errors in the designed circuits. The evaluation results show that at the end of the laboratory exercises, there was no longer a difference in knowledge between the students without prior VHDL experience and the other students. The results encourage us to continue using SHDL, and to complement the traditional DESD teaching methods with e-learning.

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Section: Hardware Description Learning Tools Existing Digital Design ...mentioning

confidence: 99%

SHDL—A Hardware Description Language and Open-Source Web Tool for Online Digital Systems Design Teaching

2023

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“…HML [5] is a hardware modeling language based on the strict functional language ML, and has support for polymorphic types and higher-order functions. There is no direct simulation support for HML, so a description in HML has to be translated to VHDL and the translated description can then be simulated in a VHDL simulator.…”

Section: Related Workmentioning

confidence: 99%

C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell

Baaij

Kooijman

Kuper

et al. 2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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CλaSH is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. Polymorphism and higherorder functions provide a level of abstraction and generality that allow a circuit designer to describe circuits in a more natural way than possible with the language elements found in the traditional hardware description languages.Circuit descriptions can be translated to synthesizable VHDL using the prototype CλaSH compiler. As the circuit descriptions, simulation code, and test input are also valid Haskell, complete simulations can be done by a Haskell compiler or interpreter, allowing high-speed simulation and analysis.

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Hardware Synthesis Using SAFL and Application to Processor Design

Mycroft

2001

Lecture Notes in Computer Science

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We survey the work done so far in the FLaSH project (Functional Languages for Synthesising Hardware) in which the core ideas are (i) using a functional language SAFL to describe hardware computation; (ii) transforming SAFL programs using various meaning-preserving transformations to choose the area-time position (e.g. by resource duplication/sharing, specialisation, pipelining); and (iii) compiling the resultant program in a resource-aware manner (keeping the gross structure of the resulting program by a 1-1 mapping of function definitions to functional units while exploiting ease-of-analysis properties of SAFL to select an efficient mapping) into hierarchical RTL Verilog. After this survey we consider how SAFL allows some of the design space concerning pipelining and superscalar techniques to be explored for a simple processor in the MIPS style. We also explore how ideas from partial evaluation (static and run-time data) can be used to unify the disparate approaches in Hydra/Lava/Hawk and SAFL and to allow processor specialisation.

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HML, a novel hardware description language and its translation to VHDL

Cited by 43 publications

References 11 publications

SHDL—A Hardware Description Language and Open-Source Web Tool for Online Digital Systems Design Teaching

SHDL—A Hardware Description Language and Open-Source Web Tool for Online Digital Systems Design Teaching

C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell

Hardware Synthesis Using SAFL and Application to Processor Design

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