HMC-Sim: A Simulation Framework for Hybrid Memory Cube Devices

Leidel, John D.; Chen, Yong

doi:10.1109/ipdpsw.2014.164

Cited by 14 publications

(7 citation statements)

References 13 publications

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“…We evaluate our design using a low-level simulator HMC-SIM, whose goal is to provide architectural simulation frameworks the ability to begin migrating current banked DRAM memory models to stacked HMC-based designs without a reduction in simulation fidelity or functionality [19]. TABLE I shows the details of the simulation configuration.…”

Section: A Methodologymentioning

confidence: 99%

Inexpensive HMC+DRAM Hybrid Main Memory Architecture with LRU-based Data Distribution Management

Zhou

Zhang

Niu

et al. 2016

Proceedings of the 2016 International Conference on Artificial Intelligence: Technologies and Applications

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The Hybrid Memory Cube (HMC) is a 3-D-stacked DRAM architecture whose I/O interface achieves up to 320 GB/s of external bandwidth. Therefore, the HMC is a promising alternative to DDRx memory due to its potential to achieve substantially improved memory bandwidth. However, the high price of a HMC device compromises cost efficiency when the device is lightly utilized. The cost of a HMC device with 2GB capacity is about 5 times of a DDRx memory with the same capacity. In this paper, we propose a new inexpensive HMC+DRAM hybrid main memory architecture to reduce the cost consumption. In order to manage such hybrid memories, we develop a LRU-based data distribution mechanism to determine the destination of particular data flow. Evaluations show that our scheme reduces the cost consumption of Main Memory by 48% on average with a negligible performance degradation compared to a current HMC-based system. Also, our architecture outperforms a current DRAM-based system by 1.5 times, and reduces the response delay by 1.2 times.

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Section: A Methodologymentioning

confidence: 99%

Inexpensive HMC+DRAM Hybrid Main Memory Architecture with LRU-based Data Distribution Management

Zhou

Zhang

Niu

et al. 2016

Proceedings of the 2016 International Conference on Artificial Intelligence: Technologies and Applications

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show abstract

“…These range from statistics counters and variable-latency links to cache and memory simulators. SST can also interface with external libraries and includes support for libraries like DRAMSim2 [16], METIS [10], and HMC-Sim [11,12]. Finally, SST is designed to be scalable through the use of thread-safe data structures, MPI communication libraries, and support for checkpointing.…”

Section: Sstmentioning

confidence: 99%

Combining Emulation and Simulation to Evaluate a Near Memory Key/Value Lookup Accelerator

Landgraf,

Lloyd,

Gokhale

2021

Preprint

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“…The detailed execution time and power information for these layers are captured by using NVprofiler [54] and Nvidia-smi [66]. From the simulator side, we leverage NVprofile to collect the event trace from host and pass it to a modified HMC-sim 3.0 [67] to simulate the computing and memory accesses in HMC. Considering that HMC-sim 3.0 cannot provide precise execution cycles and power information for the logic layer design, we conduct a gate-level simulation on Cadence [68] to measure the execution latency and power consumption for our logic design (PE).…”

Section: Evaluations 61 Experimental Setupmentioning

confidence: 99%

Enabling Highly Efficient Capsule Networks Processing Through A PIM-Based Architecture Design

Zhang

Song

Xie

et al. 2020

2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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In recent years, the CNNs have achieved great successes in the image processing tasks, e.g., image recognition and object detection. Unfortunately, traditional CNN's classification is found to be easily misled by increasingly complex image features due to the usage of pooling operations, hence unable to preserve accurate position and pose information of the objects. To address this challenge, a novel neural network structure called Capsule Network has been proposed, which introduces equivariance through capsules to significantly enhance the learning ability for image segmentation and object detection. Due to its requirement of performing a high volume of matrix operations, CapsNets have been generally accelerated on modern GPU platforms that provide highly optimized software library for common deep learning tasks. However, based on our performance characterization on modern GPUs, CapsNets exhibit low efficiency due to the special program and execution features of their routing procedure, including massive unshareable intermediate variables and intensive synchronizations, which are very difficult to optimize at software level. To address these challenges, we propose a hybrid computing architecture design named PIM-CapsNet. It preserves GPU's on-chip computing capability for accelerating CNN types of layers in CapsNet, while pipelining with an off-chip in-memory acceleration solution that effectively tackles routing procedure's inefficiency by leveraging the processing-in-memory capability of today's 3D stacked memory. Using routing procedure's inherent parallellization feature, our design enables hierarchical improvements on CapsNet inference efficiency through minimizing data movement and maximizing parallel processing in memory. Evaluation results demonstrate that our proposed design can achieve substantial improvement on both performance and energy savings for CapsNet inference, with almost zero accuracy loss. The results also suggest good performance scalability in optimizing the routing procedure with increasing network size.

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HMC-Sim: A Simulation Framework for Hybrid Memory Cube Devices

Cited by 14 publications

References 13 publications

Inexpensive HMC+DRAM Hybrid Main Memory Architecture with LRU-based Data Distribution Management

Inexpensive HMC+DRAM Hybrid Main Memory Architecture with LRU-based Data Distribution Management

Combining Emulation and Simulation to Evaluate a Near Memory Key/Value Lookup Accelerator

Enabling Highly Efficient Capsule Networks Processing Through A PIM-Based Architecture Design

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