HLS-Based Performance and Resource Optimization of Cryptographic Modules

Silitonga, Arthur; Schade, Florian; Jiang, Guanru; Becker, Juergen

doi:10.1109/bdcloud.2018.00147

Cited by 12 publications

(4 citation statements)

References 14 publications

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“…For ciphers such as AES, studies on hardware implementations have been presented [1], [6], but for ChaCha ciphers, publications such as [7] mostly describe optimizations for efficient software implementations. To the best of our knowledge, there are three hardware implementations of the ChaCha cipher: A commercial ChaCha20 implementation by Xiphera, Inc. [8].…”

Section: Related Workmentioning

confidence: 99%

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A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s

Pfau

Reuter

Harbaum

et al. 2019

2019 32nd IEEE International System-on-Chip Conference (SOCC)

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AES (Advanced Encryption Standard) accelerators are commonly used in high-throughput applications, but they have notable resource requirements. We investigate replacing the AES cipher with ChaCha ciphers and propose the first ChaCha FPGA implementations optimized for data throughput. In consequence, we compare implementations of three different system architectures and analyze which aspects dominate the performance of those.Our experimental results indicate that a bandwidth of 175 Gbit/s can be reached with as little as 2982 slices, whereas comparable state of the art AES accelerators require 10 times as many slices [1]. Taking advantage of the flexibility inherent in the ChaCha cipher, we also demonstrate how our implementation scales to even higher throughputs or lower resource usage (down to 476 slices), benefiting applications which previously could not employ cryptography because of resource limitations.

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Section: Related Workmentioning

confidence: 99%

“…There's one drawback to this approach though: In the final round, the outputs can be directly obtained at the quarter-round output port. However, as the final round is a diagonal round, the matrix elements will be emitted in the order (0, 5, 10, 15), (1,6,11,12), etc.…”

Section: B Block Memory and Register Implementationsmentioning

confidence: 99%

A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s

Pfau

Reuter

Harbaum

et al. 2019

2019 32nd IEEE International System-on-Chip Conference (SOCC)

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show abstract

“…Therefore, it is desirable to implement image processing with high computational load in hardware (1)(2)(3) . To reduce the development burden of image processing hardware, FPGA and High-Level Synthesis (HLS) (4)(5)(6) are effective because FPGA can rewrite any digital circuits many times, and HLS can automatically turn software description into hardware description.…”

Section: Introductionmentioning

confidence: 99%

Development of a Simple Verification Environment Using FPGA for image processing Hardware Created by High-Level-Synthesis Using TCP/IP

Shojima

Yamawaki

2021

The Proceedings of the 8th International Conference on Intelligent Systems and Image Processing 2021

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“…The second validation set is composed of 11 floating-point kernels, and 5 kernels with integer and bitwise operations. The floating-point kernels are from the PolyBench benchmark, and the non-floating-point kernels are from an AES security module for FP-GAs that provides data and design confidentiality (SILITONGA et al, 2018). The AES module is part of a support system that does not compose the main application to be mapped on the FPGA.…”

Section: Second Validation: Resource and Timing-aware Explorationmentioning

confidence: 99%

Lina: a fast design optimisation tool for software-based FPGA programming

Perina¹

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A contínua jornada da indústria de semicondutores levou ao desenvolvimento de diversas arquiteturas alternativas para uma computação eficiente. "Field-Programmable Gate Arrays" (FPGAs) e "Graphics Processing Units" (GPUs) são exemplos de dispositivos utilizados para acelerar aplicações. FPGAs são capazes de oferecer um paralelismo massivo para tarefas adequadas quando apropriadamente programados. No entanto, projetar para FPGA não é trivial e requer um conhecimento específico que foge do desenvolvimento usual em software. Como uma alternativa buscando aumentar a programabilidade, ferramentas de Síntese de Alto Nível (do inglês "High-Level Synthesis", ou HLS) permitem o uso de linguagens de alto-nível como C/C++/OpenCL para programar FPGAs. No entanto, experimentos preliminares e outros estudos na literatura demonstram que ainda são necessárias diversas modificações no código de alto nível para que os resultados sejam minimamente aceitáveis. Tal aspecto mitiga a democratização e simplificação propostas pelas ferramentas HLS. A contribuição principal desta tese considera C/C++ como linguagem de entrada HLS, e é composta por uma ferramenta de exploração de espaço de projeto acoplada à um estimador denominado Lina. Baseado no estimador Lin-analyzer, Lina usa a execução instrumentada de um código em alto-nível para aproximar o método de compilação do Vivado HLS, um compilador HLS C/C++ para FPGAs da Xilinx. Para um dado kernel C/C++, Lina calcula uma rápida estimativa para métricas de tempo de execução e recursos de FPGA ocupados. Junto com diretivas de otimização usadas pelo compilador HLS que o Lina também suporta, a metodologia aqui proposta permite a otimização não apenas do tempo de execução, mas também de recursos lógicos de FPGA. Considerando 16 kernels C/C++ do benchmark PolyBench, as soluções estimadas como ótimas pelo Lina estiveram dentro de 1% das melhores opções consideradas. Uma média de 14 − 16× de speedup de performance foi atingida, o que representa 70% do valor máximo alcançável considerando os espaços de projeto explorados. Adicionalmente, Lina suporta a exploração de transações com memórias off-chip em busca de otimizações como coalescência, empacotamento de dados, ou até informar sobre potenciais limitações do compilador HLS que possam degradar a performance.Palavras-chave: FPGA, Síntese de alto nível, Exploração de espaço de projeto, Exploração sem síntese de projeto.

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HLS-Based Performance and Resource Optimization of Cryptographic Modules

Cited by 12 publications

References 14 publications

A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s

A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s

Development of a Simple Verification Environment Using FPGA for image processing Hardware Created by High-Level-Synthesis Using TCP/IP

Lina: a fast design optimisation tool for software-based FPGA programming

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