HLS-based fault tolerance approach for SRAM-based FPGAs

Lojda, Jakub; Podivinsky, Jakub; Krcma, Martin; Kotásek, Zdenĕk

doi:10.1109/fpt.2016.7929561

Cited by 4 publications

(2 citation statements)

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“…Fig. 6 shows comparison results of the average Hamming distances when errors occur calculated by (11) for each design. The average Hamming distance converged to around 24 bits in all the designs as the frequency was increased.…”

Section: Resultsmentioning

confidence: 99%

“…Since introducing redundancy can cause speed performance degradation, a method to mitigate it using partial reconfiguration has also been proposed [9]. In addition, there are research reports on redundant design using HLS from the viewpoint of design productivity [10,11]. However, the targets of these work are homogeneous redundant designs, and the tolerance for common cause fault is not considered.…”

Section: Related Workmentioning

confidence: 99%

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Evaluation of Directive-based Heterogeneous Redundant Design Approaches for Functional Safety Systems on FPGAs

Saikai

Miyata

Manabe

et al. 2022

IJNC

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Field programmable gate arrays (FPGAs) are now used in a wide range of application fields including aerospace, medical, and industrial infrastructure systems, where not only soft errors but also common cause faults must be treated in systems design. Although the heterogeneous redundant design is preferable in such application fields, it tends to be a large burden on system designers. Even with high-level synthesis (HLS) technologies, which have enabled productive design processes without register transfer level (RTL) descriptions, an efficient design approach for redundant design is not always clear. In this paper, we present and evaluates two heterogeneous redundant circuit design approaches for FPGAs: a resource-level approach and strategy-level approach. The resource-level approach focuses on diversity in FPGA technology mapping. For example, two different implementations for a multiplier, one with look-up tables (LUTs) and the other with digital signal processing (DSP) blocks, can form heterogeneous redundancy. The strategylevel approach makes the use of the optimization options offered by an FPGA design tool, called strategies, as a source of diversity. For example, two different implementations can be derived from the same hardware description with area oriented optimization and performance oriented optimization. With both approaches, heterogeneous implementation variants can be generated from the same hardware description code. For evaluation, we implemented homogeneous and heterogeneous redundant designs for proportional-integralderivative (PID) control with those approaches and evaluated their error detection capability and reliability with overclock simulation. The resource-level approach showed that heterogeneous redundant designs by the proposed method have a high error detection rate in both RTL and HLS implementations in an application-level circuit. Although the detection rate of the strategy-level approach was not as high as that of the resource-level one, it was shown to have a certain diversification effect.

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Section: Resultsmentioning

confidence: 99%