HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE

UniLogic (unified logic)

“…The deviation from the ideal 4x mainly appears as we move from 3 to 4 accelerators, as the maximum sustained memory bandwidth gets reached, revealing a memory bandwidth limit of the deployed MPSoC devices at about 9 GBytes/sec. The best performance we can achieve is 7.97 sec (equivalent to 73.3 GFLOPS), which is reported in [49] and is about 2.5 times better than our prior reported results in [72], demonstrating a significant improvement over our previous single-FPGA implementation of the UNILOGIC architecture. accelerators that are not so data hungry, would benefit from higher frequencies, as would be the case when mixing data-bound and computation-bound accelerators.…”

“…This oneto-many solution has been already implemented and tested. We have successfully used it on our first, proof-of-concept, single FPGA prototype [72]. Some analysis on this will be presented in the evaluation section 6, however it is important to note here that we have even analyzed hardware architecture realizations with up to 12 accelerators controlled by a single scheduler, with encouraging results.…”

“…The initial evaluation results, that proved the feasibility of our approach, were based on a commercial board hosting a single-MPSoC and are presented in [72], while part of these can be found in Appendix D. In this part of the thesis, we report execution results for accelerators that implement the Michelsen algorithm, which is used in the calculation of the Rachford-Rice The early phase of our work, included in our first publications, confirmed that the UNILOGIC architecture can, indeed, be effectively implemented in today's reconfigurable MPSoCs; even a very simple implementation on a single device triggered a 30% speedup over a quad-core Intel-i5 CPU and more than 2x reduction in energy consumption.…”

“…The initial transition from a fully-unoptimized to a first-level optimization stage is reported in [72] and constitutes the starting point in this section. At that time, commercial single-FPGA boards was used, manufactured by Trenz Electronic GmbH and deploying the exact same FPGA, yet at that time provided only as engineering samples.…”

“…Therefore, the process has been to start off with an initial set of directives as well as code modifications introduced manually that improve the performance of the OpenCL kernels. Consequently, further exploration steps have been performed automatically using the ECOSCALE Design Space Exploration [56] (DSE) tool, which has been developed by Politecnico di Torino, and our joined efforts on its exploitation are reported in [72]. The latter has been used to enable automated design space exploration and micro-architecture definition without requiring the designer to specifically know the architectural features of the underlying FPGA.…”