HIPA&lt;sup&gt;cc&lt;/sup&gt;: A Domain-Specific Language and Compiler for Image Processing

Membarth, Richard; Reiche, Oliver; Hannig, Frank; Teich, Jürgen; Korner, Mario; Eckert, Wieland

doi:10.1109/tpds.2015.2394802

Cited by 92 publications

(39 citation statements)

References 21 publications

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“…Shallowly embedded DSLs like HIPA cc [Membarth et al 2016] or SYCL, on the other hand, do not have the cited downsides but usually rely on a modified compiler of the host language to achieve performance. In this setting, the modified compiler recognizes domain-specific patterns and manipulates the program representation.…”

Section: Dsl Embeddingmentioning

confidence: 99%

AnyDSL: a partial evaluation framework for programming high-performance libraries

Leißa

Boesche

Hack

et al. 2018

Proc. ACM Program. Lang.

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This paper advocates programming high-performance code using partial evaluation. We present a clean-slate programming system with a simple, annotation-based, online partial evaluator that operates on a CPS-style intermediate representation. Our system exposes code generation for accelerators (vectorization/parallelization for CPUs and GPUs) via compiler-known higher-order functions that can be subjected to partial evaluation. This way, generic implementations can be instantiated with target-specific code at compile time. In our experimental evaluation we present three extensive case studies from image processing, ray tracing, and genome sequence alignment. We demonstrate that using partial evaluation, we obtain high-performance implementations for CPUs and GPUs from one language and one code base in a generic way. The performance of our codes is mostly within 10%, often closer to the performance of multi man-year, industry-grade, manuallyoptimized expert codes that are considered to be among the top contenders in their fields. CCS Concepts: • Software and its engineering → Compilers; Parallel programming languages; • Hardware → Emerging languages and compilers; • Computing methodologies → Image processing; Ray tracing; • Applied computing → Bioinformatics;

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Section: Dsl Embeddingmentioning

confidence: 99%

AnyDSL: a partial evaluation framework for programming high-performance libraries

Leißa

Boesche

Hack

et al. 2018

Proc. ACM Program. Lang.

Self Cite

View full text Add to dashboard Cite

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“…PetaBricks aims at performance portability across devices, by providing a framework that allows programmers to describe multiple ways to solve a problem, while an autotuner determines the best suitable implementation for a given target platform. HIPAcc is another DSL for image processing based on source‐to‐source compilation. The authors find that domain‐specific abstractions allow mapping the algorithms to various architectures and taking advantage of different types of parallelism.…”

Section: Related Workmentioning

confidence: 99%

Dataflow management, dynamic load balancing, and concurrent processing for real‐time embedded vision applications using Quasar

Goossens

2018

Circuit Theory & Apps

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Programming modern embedded vision systems brings various challenges, due to the steep learning curve for programmers and the different characteristics of the devices. Quasar, a new high-level programming language and development environment, considerably simplifies the development. Quasar has a compiler that detects and optimizes parallel programming patterns and a heterogeneous runtime that distributes the computational load over the available compute devices (CPUs and Graphical Processing Unit [GPUs]). In this paper, we focus on runtime aspects of Quasar. We show that with good approximation, the execution time of a GPU kernel function can be factorized in a compile-time-specific component and a runtime-specific component. We show that this approximation leads to a computationally simple runtime load balancing rule. Moreover, the load balancing rule permits efficient implicit concurrency of kernel functions and automatic scaling to multiple compute devices (eg, multi-CPU/GPU systems). Based on an appropriate mathematical scheduling model, we investigate the command queue size trade-off between memory usage and device utilization. The result is a programming environment for embedded vision systems for which automatic parallelization and implicit concurrency detection allow scaling the program efficiently to multi-CPU/GPU systems. Finally, benchmark results are provided to demonstrate the performance of our approach compared with OpenACC and CUDA (Compute Unified Device Architecture).

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“…HIPAcc [21] provides native support for multigrid methods by offering appropriate language elements [22]. It generates low-level accelerator such as CUDA, OpenCL and Renderscript code from a DSL embedded into C ++ and was recently extended to emit code that can be processed to IP cores using Vivado HLS [23].…”

Section: Related Workmentioning

confidence: 99%

Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution

Schmitt

Schmid

Kuckuk

et al. 2018

Parallel Process. Lett.

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Not only in the field of high-performance computing (HPC), field programmable gate arrays (FPGAs) are a soaringly popular accelerator technology. However, they use a completely different programming paradigm and tool set compared to central processing units (CPUs) or even graphics processing units (GPUs), adding extra development steps and requiring special knowledge, hindering widespread use in scientific computing. To bridge this programmability gap, domain-specific languages (DSLs) are a popular choice to generate low-level implementations from an abstract algorithm description. In this work, we demonstrate our approach for the generation of numerical solver implementations based on the multigrid method for FPGAs from the same code base that is also used to generate code for CPUs using a hybrid parallelization of MPI and OpenMP. Our approach yields in a hardware design that can compute up to 11 V-cycles per second with an input grid size of 4096 × 4096 and solution on the coarsest using the conjugate gradient (CG) method on a mid-range FPGA, beating vectorized, multi-threaded execution on an Intel Xeon processor.

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HIPA<sup>cc</sup>: A Domain-Specific Language and Compiler for Image Processing

Cited by 92 publications

References 21 publications

AnyDSL: a partial evaluation framework for programming high-performance libraries

AnyDSL: a partial evaluation framework for programming high-performance libraries

Dataflow management, dynamic load balancing, and concurrent processing for real‐time embedded vision applications using Quasar

Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution

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