HILL: A Hardware Isolation Framework Against Information Leakage on Multi-Tenant FPGA Long-Wires

Luo, Yukui; Xu, Xiaolin

doi:10.1109/icfpt47387.2019.00060

Cited by 20 publications

(4 citation statements)

References 3 publications

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“…It should be noted that the same tests were repeated with measurement periods of 2 19 and 2 23 clock cycles, as well as with ROs made up of three inverters or one inverter and two buffers, and the results remained within 0.1-13% of each other, depending on the device. Finally, it is also worth highlighting that the extent of the information leakage seems to be broadly correlated with the size of the FPGA chip, with wires in larger, higher-end devices generally being less susceptible to information leakage (subject to process variations between and within boards of the same family).…”

Section: Medium-wire Leakagementioning

confidence: 94%

“…This suggests electrical and/or physical differences in their characteristics. It is worth noting that the threats posed by long-wire leakage have prompted defense frameworks [19,24]. These countermeasures are discussed in Section 6, along with their limitations against the new sources of information leakage introduced in this paper.…”

Section: Long-wire Leakagementioning

confidence: 99%

“…Countermeasures for long-wire leakage prevent security-critical wires from being routed adjacent to attacker wires [7,8]. HILL [19] is such a framework implementing the isolation of security-sensitive long wires. Based on user input, HILL places and routes modules so that they do not use long wires that could be possibly exposed to attackers.…”

Section: Countermeasuresmentioning

confidence: 99%

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Information leakage from FPGA routing and logic elements

Giechaskiel

Szefer

2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Medium-wire Leakagementioning

confidence: 94%

Section: Long-wire Leakagementioning

confidence: 99%

Section: Countermeasuresmentioning

confidence: 99%

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Information leakage from FPGA routing and logic elements

Giechaskiel

Szefer

2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…[16]- [19]. It can be summarized as follows: 1) Enabled by FPGA virtualization, multiple users co-reside on an FPGA chip and there is no physical interaction between the circuits of different users, and these circuits can execute simultaneously [20]. 2) All users of the same cloud-FPGA chip share certain hardware resources like the power distribution network (PDN).…”

Section: Introductionmentioning

confidence: 99%

DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA

Luo

Gongye

Fei

et al. 2021

2021 58th ACM/IEEE Design Automation Conference (DAC)

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As Field-programmable gate arrays (FPGAs) are widely adopted in clouds to accelerate Deep Neural Networks (DNN), such virtualization environments have posed many new security issues. This work investigates the integrity of DNN FPGA accelerators in clouds. It proposes DeepStrike, a remotelyguided attack based on power glitching fault injections targeting DNN execution. We characterize the vulnerabilities of different DNN layers against fault injections on FPGAs and leverage time-to-digital converter (TDC) sensors to precisely control the timing of fault injections. Experimental results show that our proposed attack can successfully disrupt the FPGA DSP kernel and misclassify the target victim DNN application.

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Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Glamočanin,

Shrivastava,

Yao

et al. 2023

J Hardw Syst Secur

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Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring instruments. In this work, however, we analyze the CPU instruction-level power side-channel leakage in an environment that lacks physical access or expensive measuring equipment. We show that instruction leakage is present even in a multitenant FPGA scenario, where the victim uses a soft-core CPU, and the adversary deploys on-chip voltage-fluctuation sensors. Unlike previous remote power side-channel attacks, which either require a considerable number of victim traces or attack large victim circuits such as machine learning accelerators, we take an evaluator’s point of view and provide an analysis of the instruction-level power side-channel leakage of a small open-source RISC-V soft processor core. To investigate whether the power side-channel traces leak secrets, we profile the victim device and implement various instruction opcode classifiers based on both classical machine learning algorithms used in disassembly attacks, and novel, deep learning approaches. We explore how parameters such as placement, trace averaging, profiling templates, and different FPGA families (including a cloud-scale FPGA) impact the classification accuracy. Despite the limited leakage of the soft-core CPU victim and a reduced accuracy and sampling rate of on-chip sensors, we show that in a worst-case scenario for the evaluator, i.e., an attacker breaching physical separation, we can identify the opcode of executed instructions with an average accuracy as high as 86.46%. Our analysis shows that determining the executed instruction type is not a classification bottleneck, while leakages between instructions of the same type can be challenging for deep learning models to distinguish. We also show that the instruction-level leakage is significantly reduced in a cloud-scale FPGA scenario with higher soft-core CPU frequencies. Nevertheless, our results show that even small circuits, such as soft-core CPUs, leak potentially exploitable information through on-chip power side channels, and users should deploy mitigation techniques against disassembly attacks to protect their proprietary code and data.

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HILL: A Hardware Isolation Framework Against Information Leakage on Multi-Tenant FPGA Long-Wires

Cited by 20 publications

References 3 publications

Information leakage from FPGA routing and logic elements

Information leakage from FPGA routing and logic elements

DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

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