Highly-reliable TaOx reram technology using automatic forming circuit

This paper proposes small array area and memory error tolerant resistive random access memory (ReRAM) computation-in-memory (CiM) with hyperparameter optimization based on bit-error rate (BER) and bit precision of log-encoding simulated annealing (SA). For combinatorial optimization problems, the proposed ReRAM CiM with log-encoding SA reduces the array area by 97.6%, compared with the conventional linear-encoding. To analyze ReRAM device error characteristics, “0” and “1” error injection is applied. The asymmetric ReRAM error improves the acceptable BER by 10 times and the acceptable bit precision to 4 bit. By adjusting the random flips and a cooling parameter, the numbers of flips and iterations decrease by 40% and 33%, respectively. Error injected (EI) iteration is changed to reproduce bit-error due to read disturb. The delay of EI iteration increases the acceptable BER by 25%. Furthermore, in the case of requiring extremely high accuracy, hyperparameter optimization improves the probability of obtaining the optimal answer by 1%.

Section: Co-design Reram Device and Log-encoding Samentioning

confidence: 99%

97.6% array area reduction, ReRAM computation-in-memory with hyperparameter optimization based on memory bit-error rate and bit precision of log-encoding simulated annealing

Misawa

Taoka

Matsui

et al. 2022

“…Figure 3(a) shows the structure of TaO X -based ReRAM, which is one example of NVM-suitable candidates. [20][21][22][23] The weights of ViT fine-tuned and quantized by the proposed three designs are stored in NVM. Figure 3(b) shows measured ReRAM current distributions of 8 Kbit cells at room temperature.…”

Section: Introductionmentioning

confidence: 99%

Design methodology of compact edge vision transformer CiM considering non-volatile memory bit precision and memory error tolerance

Misawa,

Yamaguchi,

Yamada

et al. 2024

This paper proposes a design methodology for a compact edge vision transformer (ViT) Computation-in-Memory (CiM). ViT has attracted much attention for its high inference accuracy. However, to achieve high inference accuracy, the conventional ViT requires fine-tuning many parameters with pre-trained models on large datasets and a large number of matrix multiplications in inference. Thus, to map ViT to non-volatile memory (NVM)-based CiM compactly for edge applications (IoT/Mobile devices) in inference, this paper analyses fine-tuning in training, clipping, and quantization in inference. The proposed compact edge ViT CiM can be optimized by three design methods according to use cases considering the required fine-tuning time, ease of setting memory bit precision, and memory error tolerance of ViT CiM. As a result, in CIFAR-10, the most compact type successfully reduces the total memory size of ViT by 85.8% compared with the conventional ViT. Furthermore, the high accuracy type and high error-tolerant type improve inference accuracy by 4.4% and memory-error tolerance by more than four times compared with convolutional neural networks, respectively.

“…In the bottom of this multiple-tier network system, high-capacity but long-latency three-dimensional (3D) triple-level cell (TLC, 3 bit/cell) NAND flash memory 3,4) is utilized to store high-capacity image/sensor data. In cloud centralized servers of the top tier, in contrast, resistive RAM (ReRAM) [5][6][7] stores model/weight data for machine learning to share with the other cloud centralized servers and distribute to the edge servers. The model is a neural network itself, which contains information such as the number of layers and how the layers are connected.…”

Section: Introductionmentioning

confidence: 99%

Non-volatile memory system design of edge server and cloud centralized server for multiple-tier 5G network

Matsui¹,

Takeuchi²

2021

This paper co-designs a network and non-volatile memory system for a fifth generation (5G) multiple-tier network. Because a 5G network has shorter latency and wider bandwidth compared with a 4G network, the non-volatile memory system becomes a bottleneck. From the bottom to the top of the multiple-tier network, edge devices/machines, edge servers, and cloud centralized servers play different types of roles and handle different types of data. Thus, different types of non-volatile memory are required for cloud centralized servers, edge servers, and edge devices/machines. This work employs three-dimensional single-level cell (3D-SLC) NAND flash memory for edge servers and resistive RAM (ReRAM) for cloud centralized servers. To achieve short latency and low cost of the non-volatile memory system, distributed multiple write for 3D-SLC NAND flash memory and hierarchical multiple-deck ReRAM are proposed. By using an evaluation platform of the network and non-volatile memory co-design system, the proposed non-volatile memory system is defined as a network bottleneck or memory bottleneck.