Highly reliable TaO&lt;inf&gt;x&lt;/inf&gt; ReRAM with centralized filament for 28-nm embedded application

Hayakawa, Y.; Himeno, A.; Yasuhara, Ryo; Boullart, Werner; Vecchio, E.; Vandeweyer, T.; Witters, T.; Crotti, D.; Jurczak, M.; Fujii, Satoshi; Ito, Satoru; Kawashima, Y.; Ikeda, Y.; Kawahara, Akifumi; Kawai, K.; Wei, Zhigiang; Muraoka, S.; Shimakawa, K.; Mikawa, Takumi; Yoneda, Shigeo

doi:10.1109/vlsit.2015.7223684

Cited by 54 publications

(47 citation statements)

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“…[82][83][84] Both HfO x /TaO x -based RRAM show excellent resistive behavior. [85][86][87][88][89] Besides, they have the potential to form a multi-bit memory cell. 90,91 The typical unipolar and bipolar I-V characteristics of RRAM are shown in Figure 8A,B.…”

Section: Materials Selectionmentioning

confidence: 99%

“…116 Hayakawa et al demonstrated a TaO x RRAM with precise filament positioning by forming an encapsulated cell structure. 87 Li et al reported a reduction of variation and forming/set voltage can be achieved through enhanced electrical field by a pyramid-like electrode. 117 In addition, the set/reset voltage and corresponding low/high resistance states have mutual and accumulative influences on their counterparts as well as subsequent switching cycles.…”

Section: Uniformitymentioning

confidence: 99%

See 1 more Smart Citation

Memory materials and devices: From concept to application

Zhang

Wang

Shi

et al. 2020

InfoMat

197

141

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Memory cells have always been an important element of information technology. With emerging technologies like big data and cloud computing, the scale and complexity of data storage has reached an unprecedented peak with a much higher requirement for memory technology. As is well known, better data storage is mostly achieved by miniaturization. However, as the size of the memory device is reduced, a series of problems, such as drain gate‐induced leakage, greatly hinder the performance of memory units. To meet the increasing demands of information technology, novel and high‐performance memory is urgently needed. Fortunately, emerging memory technologies are expected to improve memory performance and drive the information revolution. This review will focus on the progress of several emerging memory technologies, including two‐dimensional material‐based memories, resistance random access memory (RRAM), magnetic random access memory (MRAM), and phase‐change random access memory (PCRAM). Advantages, mechanisms, and applications of these diverse memory technologies will be discussed in this review.

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Section: Materials Selectionmentioning

confidence: 99%

Section: Uniformitymentioning

confidence: 99%

Memory materials and devices: From concept to application

Zhang

Wang

Shi

et al. 2020

InfoMat

197

141

View full text Add to dashboard Cite

show abstract

“…To address the sneak path issue, a select device connected in series with memristor is required, such as a transistor or a selector, which therefore forms a 1 transistor 1 resistor (1T1R) or 1 selector 1 resistor (1S1R) structure, or on‐state nonlinearity needs to be introduced into the memristive device itself . Figure (c) shows structure and die micrograph of a 2 Mb 1T1R memristor array using 28 nm technology . However, the introduction of transistors increased the feature size compared with passive arrays.…”

Section: Memristive Crossbar Arraymentioning

confidence: 99%

Section: Memristive Crossbar Arraymentioning

confidence: 99%

Memristive Devices and Networks for Brain‐Inspired Computing

Zhang

et al. 2019

Physica Rapid Research Ltrs

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As the era of big data approaches, conventional digital computers face increasing difficulties in performance and power efficiency due to their von Neumann architecture. As a result, there is recently a tremendous upsurge of investigations on brain-inspired neuromorphic hardware with high parallelism and improved efficiency. Memristors are considered as promising building blocks for the realization of artificial synapses and neurons and can therefore be utilized to construct hardware neural networks. Here, a review is provided on existing approaches for the implementation of artificial synapses and neurons based on memristive devices; and the respective advantages and disadvantages of these approaches are evaluated. This is followed by a discussion of hardware accelerators and neuromorphic computing systems that exploit the parallel, in-memory and analog characteristics of memristive crossbar arrays as well as the intrinsic dynamics of memristors. Finally, the outstanding challenges are addressed that have not yet been resolved in the present studies, and future advances are discussed that might be needed for building intelligent and energy efficient neuromorphic systems.

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“…We distinguish between mediumdensity embedded memristor applications and high-density storage-class memory (SCM). Memristors in PUMA use 1T1R configuration which have been shown to have good manufacturability [50]. They are very different from SCM, where the selector transistor may be replaced with an in-line twoterminal selector device for higher density which complicates manufacturability.…”

Section: Related Workmentioning

confidence: 99%

Puma

Ankit

Hajj

Chalamalasetti

et al. 2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

259

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Memristor crossbars are circuits capable of performing analog matrix-vector multiplications, overcoming the fundamental energy efficiency limitations of digital logic. They have been shown to be effective in special-purpose accelerators for a limited set of neural network applications.We present the Programmable Ultra-efficient Memristorbased Accelerator (PUMA) which enhances memristor crossbars with general purpose execution units to enable the acceleration of a wide variety of Machine Learning (ML) inference workloads. PUMA's microarchitecture techniques exposed through a specialized Instruction Set Architecture (ISA) retain the efficiency of in-memory computing and analog circuitry, without compromising programmability.We also present the PUMA compiler which translates high-level code to PUMA ISA. The compiler partitions the computational graph and optimizes instruction scheduling and register allocation to generate code for large and complex workloads to run on thousands of spatial cores.We have developed a detailed architecture simulator that incorporates the functionality, timing, and power models of * Work done while at University of Illinois at Urbana-Champaign PUMA's components to evaluate performance and energy consumption. A PUMA accelerator running at 1 GHz can reach area and power efficiency of 577 GOPS/s/mm 2 and 837 GOPS/s/W, respectively. Our evaluation of diverse ML applications from image recognition, machine translation, and language modelling (5M-800M synapses) shows that PUMA achieves up to 2,446× energy and 66× latency improvement for inference compared to state-of-the-art GPUs. Compared to an application-specific memristor-based accelerator, PUMA incurs small energy overheads at similar inference latency and added programmability.

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Highly reliable TaO<inf>x</inf> ReRAM with centralized filament for 28-nm embedded application

Cited by 54 publications

References 0 publications

Memory materials and devices: From concept to application

Memory materials and devices: From concept to application

Memristive Devices and Networks for Brain‐Inspired Computing

Puma

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