Highly reliable molecular-pore-stacking (MPS)/Cu interconnects featuring best combination of post-etching treatment and resputtering processes

Oshida, Daisuke; Kume, I.; Katsuyama, Hirokazu; Ueki, Makoto; Iguchi, Manabu; Yokogawa, Shinji; Inoue, N.; Oda, Noriaki; Sakurai, Michio

doi:10.1016/j.mee.2013.12.007

Cited by 3 publications

(1 citation statement)

References 14 publications

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“…The large hydrocarbons attached to hexagonal silica backbones in molecular‐pore‐stacked SiOCH prevent the oxidation of Si‐CH 3 during the O 2 plasma ash process, reducing the C‐depleted damage area at the sidewalls of via holes and trench lines. Oshida et al reported the effects of post‐etching treatment in trench patterning and resputtering for barrier metal sputtering on low‐k/Cu interconnects for low‐k molecular pore stacking. The optimized combination of post‐etching treatment and resputtering reduced wiring capacitance by 5% because of a well‐controlled profile that resulted from the hardening effect of the exposed porous material at the trench bottom.…”

Section: Process Optimizations and Improvementsmentioning

confidence: 99%

Review of methods for the mitigation of plasma‐induced damage to low‐dielectric‐constant interlayer dielectrics used for semiconductor logic device interconnects

Miyajima

Ishikawa

Sekine

et al. 2019

Plasma Processes & Polymers

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The developments in advanced interconnect technology for semiconductor logic devices for the mitigation of plasma‐induced damage to low‐dielectric‐constant (low‐k) materials, including fluorosilicate glass and carbon‐doped silicon oxide is reviewed. The chemical bond structures of low‐k materials are summarized to help mitigate the k value degradation caused by moisture uptake after plasma processes. Damage suppression is accomplished by integrating deposition chemistries, pattern etch transfer, and post‐etch cleaning technologies. On the basis of analyses results, a discussion on the bond engineering of low‐k materials and their degradation during plasma processing is given. Challenges facing low‐k interconnect technology are also addressed.

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Section: Process Optimizations and Improvementsmentioning

confidence: 99%

Review of methods for the mitigation of plasma‐induced damage to low‐dielectric‐constant interlayer dielectrics used for semiconductor logic device interconnects

Miyajima

Ishikawa

Sekine

et al. 2019

Plasma Processes & Polymers

View full text Add to dashboard Cite

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Reliability and Interface in Cu Interconnects: Contribution and Control of Interface for EM, SIV, and TDDB

慎二

2014

Journal of The Surface Science Society of Japan

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Survey of critical failure events in on-chip interconnect by fault tree analysis

Yokogawa

Kunii

2018

Jpn. J. Appl. Phys.

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In this paper, a framework based on reliability physics is proposed for adopting fault tree analysis (FTA) to the on-chip interconnect system of a semiconductor. By integrating expert knowledge and experience regarding the possibilities of failure on basic events, critical issues of on-chip interconnect reliability will be evaluated by FTA. In particular, FTA is used to identify the minimal cut sets with high risk priority. Critical events affecting the on-chip interconnect reliability are identified and discussed from the viewpoint of long-term reliability assessment. The moisture impact is evaluated as an external event.

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Highly reliable molecular-pore-stacking (MPS)/Cu interconnects featuring best combination of post-etching treatment and resputtering processes

Cited by 3 publications

References 14 publications

Review of methods for the mitigation of plasma‐induced damage to low‐dielectric‐constant interlayer dielectrics used for semiconductor logic device interconnects

Review of methods for the mitigation of plasma‐induced damage to low‐dielectric‐constant interlayer dielectrics used for semiconductor logic device interconnects

Reliability and Interface in Cu Interconnects: Contribution and Control of Interface for EM, SIV, and TDDB

Survey of critical failure events in on-chip interconnect by fault tree analysis

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