Highly Parallel Implementation of Harris Corner Detector on CSX SIMD Architecture

Hosseini, Fouzhan; Fijany, Amir; Fontaine, Jean‐Guy

doi:10.1007/978-3-642-21878-1_17

Cited by 10 publications

(4 citation statements)

References 6 publications

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“…The authors of [29] utilize a Jetson (ARM and GPU) similar to this work, with a GPU instead of using programmable logic. The authors of [30] implement HCD on a ASIC SIMD architecture. The authors of [12] use an NoC-based MPSoC with 16 RISC cores assisted by an external ARM CPU.…”

Section: Performance Evaluationmentioning

confidence: 99%

A Manycore Vision Processor for Real-Time Smart Cameras

Silva

Lima

Arias-García

et al. 2021

Sensors

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Real-time image processing and computer vision systems are now in the mainstream of technologies enabling applications for cyber-physical systems, Internet of Things, augmented reality, and Industry 4.0. These applications bring the need for Smart Cameras for local real-time processing of images and videos. However, the massive amount of data to be processed within short deadlines cannot be handled by most commercial cameras. In this work, we show the design and implementation of a manycore vision processor architecture to be used in Smart Cameras. With massive parallelism exploration and application-specific characteristics, our architecture is composed of distributed processing elements and memories connected through a Network-on-Chip. The architecture was implemented as an FPGA overlay, focusing on optimized hardware utilization. The parameterized architecture was characterized by its hardware occupation, maximum operating frequency, and processing frame rate. Different configurations ranging from one to eighty-one processing elements were implemented and compared to several works from the literature. Using a System-on-Chip composed of an FPGA integrated into a general-purpose processor, we showcase the flexibility and efficiency of the hardware/software architecture. The results show that the proposed architecture successfully allies programmability and performance, being a suitable alternative for future Smart Cameras.

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Section: Performance Evaluationmentioning

confidence: 99%

A Manycore Vision Processor for Real-Time Smart Cameras

Silva

Lima

Arias-García

et al. 2021

Sensors

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“…An overview of the foundation of the algorithm, as described in [37] and similarly restated here, can be formulated as follows.…”

Section: The Harris Algorithm For Corner Detectionmentioning

confidence: 99%

“…The SIMD part is left to the compiler (the native one for each considered architecture), and shared memory parallelism is implemented with OpenMP (through classical directives. Other studies of Harris corner detection and its applications can be found in [35,36,37,38,39].…”

Section: Introductionmentioning

confidence: 99%

Harris corner detection on a NUMA manycore

Haggui

Tadonki

Lacassagne

et al. 2018

Future Generation Computer Systems

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Corner detection is a key kernel for many image processing procedures including pattern recognition and motion detection. The latter, for instance, mainly relies on the corner points for which spatial analyses are performed, typically on (probably live) videos or temporal flows of images. Thus, highly efficient corner detection is essential to meet the real-time requirement of associated applications. In this paper, we consider the corner detection algorithm proposed by Harris, whose the main work-flow is a composition of basic operators represented by their approximations using 3 × 3 matrices. The corresponding data access patterns follow a stencil model, which is known to require careful memory organization and management. Cache misses and other additional hindering factors with NUMA architectures need to be skillfully addressed in order to reach an efficient scalable implementation. In addition, with an increasingly wide vector registers, an efficient SIMD version should be designed and explicitly implemented. In this paper, we study a direct and explicit implementation of common and novel optimization strategies, and provide a NUMA-aware parallelization. Experimental results on a dual-socket INTEL Bradwell-E/EP show a noticeably good scalability performance.

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“…Cell Processor [64] and single instruction multiple data (SIMD) architecture [65]. In [66], a simpler floating-point format is used by customizing instructions on the Nios-II processor.…”

Section: Feature Detectionmentioning

confidence: 99%

Embedded computing techniques for remote mobile video surveillance systems

Nirmala¹

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AcknowledgementsMy journey this far in my research has been made possible by the wonderful people around me. Here is my humble attempt to express my gratitude for all their time, efforts and motivation.First, I would like to express my deepest gratitude to my supervisor Prof. Thambipillai Srikanthan for being a constant source of energy and inspiration throughout this research work, with his relentless guidance and motivation. Despite his numerous commitments, Prof. Sri ensured that he engaged with me in weekly discussions that kept up my momentum. I also appreciate him for always pushing me beyond my comfort zones that allowed me to grow as a researcher.I would like to thank Dr. Siew-Kei Lam for all the discussions to strengthen my work and his patient guidance throughout all my research publications. I am grateful to Dr. Meiqing Wu for all the brainstorming sessions and for inspiring me with the rigour she brings into her research. I would like to thank Dr. Alok Prakash for helping me during the critical phase of thesis writing. Thank you Supriya Sathyanarayana, Kratika Garg, Dr. Suchitra Sathyanarayana and Dr. Ravi Satzoda for the numerous brainstorming sessions and for making computer vision research fun. For all the technical and logistic support, I wish to thank Mr. Jeremiah Chua and Ms. Nah Kiat Joo.I am forever grateful to be blessed with the most supportive family and loving friends without whom this journey would have been impossible. Thank you Bhaskar, my pillar of strength. Thank you Amma, Appa and Sowmya, and Paatti for being there always. My friends Kavitha, Karthik, Kavitha and Deepthi, thank you.

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Highly Parallel Implementation of Harris Corner Detector on CSX SIMD Architecture

Cited by 10 publications

References 6 publications

A Manycore Vision Processor for Real-Time Smart Cameras

A Manycore Vision Processor for Real-Time Smart Cameras

Harris corner detection on a NUMA manycore

Embedded computing techniques for remote mobile video surveillance systems

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