Highly integrated InP HBT optical receivers

Yung, M.W.; Jensen, J.F.; Walden, R.H.; Rodwell, M.J.W.; Raghavan, G.; Elliott, K.; Stanchina, W.E.

doi:10.1109/4.743780

Cited by 15 publications

(10 citation statements)

References 14 publications

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“…This chip, containing over 2000 transistors, is comprised of a photodiode, transimpedance amplifier, limiting amplifier, clock and data recovery circuitry, demultiplexer and synchronization logic. 9 We also describe four-channel receiver arrays for analog photonic links. These arrays, which operate at frequency bands between 1 and 18 GHz, contain passive LR and RC filtering elements in addition to the photodetectors and transimpedance amplifiers.11 Another OEIC, a 4-bit flash analog-to-digital converter contains 4 photodiodes for the differential analog input signal and two clock inputs.10 To achieve high analog-link efficiency, the photodiodes can handle high levels of optical power and maintain their frequency response even when the average photocurrent is as high as 20 mA.…”

Section: Introductionmentioning

confidence: 99%

Integrated optoelectronic circuits with InP-based HBTs

et al. 2001

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Integrated optoelectronic circuits that are capable of very high speeds or high functionality have been demonstrated using InP-based heterojunction bipolar transistors (HBTs). Optoelectronic receivers contain photodetectors fabricated from the same epitaxial material structure as the HBTs. High-functionality digital receivers, analog receiver arrays as well as analogto-digital converters have been realized. Optoelectronic modulation circuits for signal transmission also contain separately grown, surface-coupled multiple-quantum-well (MQW) modulators.

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Section: Introductionmentioning

confidence: 99%

Integrated optoelectronic circuits with InP-based HBTs

et al. 2001

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“…The di usion of wireless and mobile communications in the last decade has determined the need for high-speed bipolar digital integrated circuits, which are usually implemented in the Current-Mode Logic (CML) style to ensure operation at frequencies ranging from several GHz to almost a hundred of GHz [1][2][3][4][5][6][7][8][9][10][11][12]. Such a high speed operation is achieved by setting the static bias current of CML gates to high values, i.e.…”

Section: Introductionmentioning

confidence: 99%

“…The delay PD for a step input of a circuit with the transfer function (1) can be simply expressed through the pole and zero time constants according to Equation (2), as demonstrated in References [19,22]…”

mentioning

confidence: 99%

Modelling and design considerations on CML gates under high-current effects

Alioto

Palumbo

2005

Int. J. Circ. Theor. Appl.

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SUMMARYIn this paper, the e ect of the transit time degradation of bipolar transistors on the power-delay tradeo in CML gates and their design is dealt with. A delay model which accounts for the transit time increase due to the high bias current values used in high-speed applications is derived by generalizing an approach previously proposed by the same authors (IEEE Trans. CAD 1999; 18(9):1369 -1375; Model and Design of Bipolar and MOS Current-Mode Logic (CML, ECL and SCL Digital Circuits), Kluwer Academic Publisher: Dordrecht, 2005). The resulting closed-form delay expression is achieved by properly simplifying the SPICE model, and has an explicit dependence on the bias current which determines the power consumption of CML gates. Accordingly, the delay model is used to gain insight into the power-delay trade-o by considering the e ect of the transit time degradation in high-speed designs. In particular, the cases where such e ects can be neglected are identiÿed, to better understand how the transit time degradation a ects the performance of CML gates for current bipolar technologies.The proposed model has a simple and compact expression, thus it turns out to be suitable for penciland-paper evaluations, as well as fast timing analysis. Simulations of CML circuits with a 20-GHz bipolar process show that the model has a very good accuracy in a wide range of current and loading conditions.

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“…In 1998 we demonstrated a fully integratted 7.5 Gbps optical receiver ASIC that monolithically integrated all the critical components, including the photo diode, the amplifier stage, the clock and data recovery circuit (CDR), the demultiplexer, and the word-synchronization logic (16). It consumed 3 W of power and consisted of 2100 transistors (Fig.…”

Section: Demonstration Circuitsmentioning

confidence: 99%

High speed, low power, optoelectronic InP-based HBT integrated circuits

Sokolich

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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The next generation of fiber optic communication systems will require circuits operating at 50 GHz clock rates. InPbased Heterojunction Bipolar Transistors (HBTs) are ideally suited for the relatively low integration levels but high speed and low power required in optoelectronic transceivers. We review material, device and circuit issues related to InP HBT and the significant challenge that exists because communication system requirements are approaching the performance limits of high speed technologies . IntroductionData transmission requirements in fiber optic systems are quickly catching up to state-of-the-art electronics. As a result, what were once considered "exotic" technologies are now being evaluated for communication system insertion. Of these, InP-based HBT technology has consistently demonstrated the highest clock rate, lowest poweddelay product and best compromise between integration level and performance for critical optical transceiver components. Recently these benchmark results have been turned into real circuits with adequate margin for 40 Gbps transmission. A few of these results have been published, others have simply been announced by press release because of the intense competition among technologies and companies that wish to be players in the 40 Gbps build out. This paper is a review and tutorial for circuit designers less familiar with InP as a technology for high speed, low power, optoelectronic applications. We will tie device performance to relevant circuit performance and contrast the capability of InP to other possible technologies. We hope to give the reader a "vertical" view of material, process, device, circuit and system level considerations that influence technology selection.

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Highly integrated InP HBT optical receivers

Cited by 15 publications

References 14 publications

Integrated optoelectronic circuits with InP-based HBTs

Integrated optoelectronic circuits with InP-based HBTs

Modelling and design considerations on CML gates under high-current effects

High speed, low power, optoelectronic InP-based HBT integrated circuits

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