Highly Efficient Reconfigurable Stateful Logic Operations Based on CuI Memristor-Only Arrays Prepared With a Solution-Based Process

Abstract

The in-memory logic computing has been intensively studied as being considered as an important scenario to address the power-consumption issue posed by modern computers based on the von Neumann architecture. However, the realization of in-memory logic computing is generally based on memristors prepared by vacuum techniques and the implementation of logic operation requires multiple cycles of voltage pulses, which limits the computing efficiency. In addition, the logic architectures that cannot be mapped into large crossbar arrays restrict the level of parallelism. A CuI memristor is prepared by a solution-based process in this work. Based on the CuI memristor arrays, with delicately designed implement strategy, a set of logic operations can be implemented with one single cycle of voltage pulses, demonstrating the high efficiency. Moreover, all proposed logic architectures are able to be mapped to large memristor crossbar arrays directly, demonstrating the great potentials in computations with high degree of parallelism. Owing to the reconfigurable property, a one-bit full adder is realized by cascading the memristor-based logic gates. CuI, high parallelism, in-memory computing, logic gate, memristor. INDEX TERMS

Implication Logic Circuit Based on a Graphene Oxide Complementary Resistive Switching Device

“…However, at present, there is still no single, accepted standard for designing logic circuits, and the memory and computing integration architecture based on memristors still needs to mature. Popular logic circuit design techniques for memristor logic circuits include [32][33][34] assisted logic (MAGIC), [35] material implication logic (IMP), [36] and memristor ratioed logic (MRL). [37] Compared with IMP logic and MRL logic, MAGIC logic composed only of memristors cannot realize cascades between multiple logic gates and multiple fanouts for structural reasons.…”