Highly efficient multi-point clock distribution networks

Abstract

This paper presents techniques for top-level high-speed clock distribution in large VLSI circuits. The techniques described resort to feedback mechanisms on the clock path, using controlled delay lines. These techniques allow the synchronization of a large number of top-level domains without extra interconnection lines, with clear performance improvements over other proposals.

Systematic Analysis of Active Clock Deskewing Systems Using Control Theory

“…This is difficult to achieve [2], [4], [6], [7]. In order to compensate for skew in real time a closed loop clock distribution system known as the active deskewing system, has been proposed by [8], [9], [1], [10], [11], [12]. Such a system exhibits disturbance rejection and is robust to modeling errors.…”