High Voltage (up to 20V) Devices Implementation in 0.13 um BiCMOS Process Technology for System-On-Chip (SOC) Design

Pan, Robert; Todd, B.; Hao, P. H.; Higgins, R.; Robinson, D.; Drobny, V.; Tian, Wei; Wang, Jianglin; Mitros, J.; Huber, M.; Pillai, S. Vijayan; Pendharkar, S.

doi:10.1109/ispsd.2006.1666143

Cited by 8 publications

(4 citation statements)

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“…This section discusses the various LDMOS design types, their key features, and tradeoffs, focusing on devices that are optimized to operate in the range 20-700 V. For very high-power applications, vertical DMOS (or IGBT) transistors are preferred [35], but these typically share a common drain when integrated on a chip and are not discussed here. [34], and 65-nm technology using dielectric RESURF [32] …”

Section: Design and Characteristics Of Ldmosmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

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Section: Design and Characteristics Of Ldmosmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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“…5. DECMOS transistors in AN180 show very competitive performance compared to 0.13 um BiCMOS technology [1]. For example, 20V DENMOS and DEPMOS have a breakdown voltage of 40V and -30V and the specific on-resistance of 44 and 55 mΩ•mm 2 , respectively.…”

Section: B De(drain-extended) Cmosmentioning

confidence: 99%

A versatile 30V analog CMOS process in a 0.18μm technology for power management application

Choi

Park

Lim

et al. 2011

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs

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a versatile 30V analog CMOS process in a 0.18 µm technology node has been developed by using cost-effective and modular fashion. To reduce the thermal budget deep NWELL isolation is formed after CMOS well formation. The drainextended (DE) CMOS from 7V to 30V shows very competitive trade-off performance between the breakdown voltage and the specific on-resistance. In addition, low 1/f noise of 5V CMOS can be obtained by pure gate oxide process.

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“…Development of battery-powered system-on-chip (SoC) circuits with high gate voltage in the sub-100nm CMOS process technology is getting more important to meet the functionality requirements of portable electronic device applications [1,2].…”

Section: Introductionmentioning

confidence: 99%

Design of multiple RESURF LDMOS with P-top rings and STI regions in 65nm CMOS technology

Lee

Sheu

Yang

et al. 2011

TENCON 2011 - 2011 IEEE Region 10 Conference

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In this work, a novel multiple RESURF P-top rings LDMOS with shallow trench isolation (STI) stucture based on the 65 nm baseline low-voltage CMOS technology by threedimentsional Sentaurus process and device simulations. A optimized uniform electric filed distribution in N-drift region can be obtained by empolying the multiple P-top rings process instead of the past proposed gate field plates method in the extended drain regions. By this way, not only both of high breakdown voltage exceeded over 40V and low on-resistance below 20 mΩ-mm 2 can be achieved, but also the effect of W Ndrift /W STI ratio on device can be reduce to otain the larger optimal window of device characteristics, as compared with the conventional DIELER and graded gate field plate devices.

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High Voltage (up to 20V) Devices Implementation in 0.13 um BiCMOS Process Technology for System-On-Chip (SOC) Design

Cited by 8 publications

References 0 publications

High-Voltage and Power Transistors

High-Voltage and Power Transistors

A versatile 30V analog CMOS process in a 0.18μm technology for power management application

Design of multiple RESURF LDMOS with P-top rings and STI regions in 65nm CMOS technology

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High Voltage (up to 20V) Devices Implementation in 0.13 um BiCMOS Process Technology for System-On-Chip (SOC) Design

Cited by 8 publications

References 0 publications

High-Voltage and Power Transistors

High-Voltage and Power Transistors

A versatile 30V analog CMOS process in a 0.18&#x03BC;m technology for power management application

Design of multiple RESURF LDMOS with P-top rings and STI regions in 65nm CMOS technology

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Product

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A versatile 30V analog CMOS process in a 0.18μm technology for power management application