High voltage LDMOS transistors in sub-micron SOI films

Paul, Kateri E.; Leung, Ying K.; Plummer, J.D.; Wong, S.S.; Kuehne, S.C.; Huang, Vincent; Nguyen, C.T.

doi:10.1109/ispsd.1996.509455

Cited by 18 publications

(4 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…8, the calculated specific on-resistance for the device was 18.8 mΩ•cm 2 with the drain current of 168 µA at V ds = 0.1 V when the area of the device was 3.15 10 -5 cm 2 . R on = 0.1 V / 168 µA 3.15 10 -5 cm 2 = 18.8 mΩ•cm 2 The specific on-resistance of 18.8 mΩ•cm 2 was lower than any other published work for SOI LDMOSFET devices [14]- [15]. Figure 10 shows the forward conduction characteristics of the proposed trench LDMOSFET.…”

Section: Si 3 N 4 Teosmentioning

confidence: 82%

A New Structure of SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

Son¹,

Kim²,

Sohn³

et al. 2004

ETRI J

View full text Add to dashboard Cite

To improve the characteristics of breakdown voltage and specific on‐resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon‐on‐insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on‐resistance. The breakdown voltage and the specific on‐resistance of the fabricated device is 352 V and 18.8 m·cm2 with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on‐state is over 200 V and the saturation current at Vgs=5 V and Vds=20 V is 16 mA with a gate width of 150 µm.

show abstract

Section: Si 3 N 4 Teosmentioning

confidence: 82%

A New Structure of SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

Son¹,

Kim²,

Sohn³

et al. 2004

ETRI J

View full text Add to dashboard Cite

show abstract

“…The two high-field effects give rise to (34), which is shown at the bottom of the page for the high-field effective mobility.…”

Section: ) Combined Mobility Modelmentioning

confidence: 99%

“…In ultrathin RESURF SOI LDMOS structures, the distribution of the heat generation in the drift region will be highly nonuniform, but will be reasonably constant in thicker SOI LDMOS devices [33], [34]. In compact models two-dimensional (2-D) heat-flow analysis [35] is too complicated, and it is usually preferred [14], [36] to assume thermal equilibrium and use an average temperature rise .…”

Section: Modelling Heating Effectsmentioning

confidence: 99%

MOOSE: A Physically Based Compact DC Model of SOI LDMOSFETs for Analogue Circuit Simulation

D'Halleweyn

Benson

Redman-White

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-In this paper, we present a compact model for silicon-on-insulator (SOI) laterally double diffused (LD) MOSFETs. The model is complete insofar as it uses no subcircuits, and is intended to predict device operation in all regions of bias. The device current is described by two main equations handling the MOS channel and the drift region, both of which are smooth and continuous in all operating regimes. Attention is also given to the modeling of inversion at the back oxide to ensure correct behavior is predicted for a source follower in power control applications ("high side operation"). A surface-potential-based formulation is used for the inversion/accumulation channel giving smooth transitions between different regions of operation, and care has been taken to ensure all expressions are smooth and infinitely differentiable to achieve the best possible convergence performance. Self (and coupled) heating effects exert a major influence over the behavior of power SOI devices, and these issues are incorporated in the model core in a consistent fashion.The model has been installed in a commercial SPICE-type circuit simulator and evaluated against individual devices and complete circuits fabricated in an industrial smart power SOI process. Accuracy is significantly improved with respect to the existing LDMOS models, and convergence behavior in switching and linear circuit simulations is comparable with industry standard models of this complexity.

show abstract

“…The approach of designing and implementing the linear doping profile on thin SOI for lateral high voltage devices was presented in 1995 [4]. A submicron thin film SOI LDMOS with the variable doping profile and numerical modeling of linear doping profiles were proposed in 1996 and 1999, respectively [5,6]. After 2000, several new SOI devices structures with linear doping profile were proposed [7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Improving Breakdown Voltage for a Novel SOI LDMOS with a Lateral Variable Doping Profile on the Top Interface of the Buried Oxide Layer

Jin

Chen

et al. 2015

Advances in Condensed Matter Physics

View full text Add to dashboard Cite

In order to achieve a high breakdown voltage (BV) for the SOI (Silicon-On-Insulator) power device in high voltage ICs, a novel high voltage n-channel lateral double-diffused MOS (LDMOS) with a lateral variable interface doping profile (LVID) placed at the interface between the SOI layer and the buried-oxide (BOX) layer (LVID SOI) is researched. Its breakdown mechanism is investigated theoretically, and its structure parameters are optimized and analyzed by 2D simulation software MEDICI. In the high voltage blocking state, the high concentration ionized donors in the depleted LVID make the surface electric field of SOI layer (ES) more uniform and enhance the electric field of BOX layer (EI), which can prevent the lateral premature breakdown and result in a higher BV. Compared with the conventional uniformly doped (UD) SOI LDMOS,EIof the optimized LVID SOI LDMOS is enhanced by 79% from 119 V/μm to 213 V/μm, and BV is increased by 33.4% from 169 V to 227 V. Simulations indicate that the method of LVID profile can significantly improve breakdown voltage for the SOI LDMOS.

show abstract

High voltage LDMOS transistors in sub-micron SOI films

Cited by 18 publications

References 6 publications

A New Structure of SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

A New Structure of SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

MOOSE: A Physically Based Compact DC Model of SOI LDMOSFETs for Analogue Circuit Simulation

Improving Breakdown Voltage for a Novel SOI LDMOS with a Lateral Variable Doping Profile on the Top Interface of the Buried Oxide Layer

Contact Info

Product

Resources

About