High voltage, high current lateral devices

Vaes, H.M.J.; Appels, J.A.

doi:10.1109/iedm.1980.189760

Cited by 30 publications

(10 citation statements)

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“…5a, the possible peak field occurs near the drain or the source with the variation of drift doping concentration. The maximum V B is realized when the [19] , (b) double RESURF LDMOS [20] , (c) triple RESURF LDMOS [21] , and (d) local charge-balanced RESURF LDMOS [22,23] .…”

Section: Resurf Technologymentioning

confidence: 99%

“…In further reducing R on,sp , the additional reverse depletion of the PN junction discussed in Section 1.1 is introduced into the single N-type doped drift region to form double and triple RESURF structures, as shown in Figs. 5b and 5c [20,21,24,25] . As the number of depletion junctions increases from 1 to 2 -3, the D op values of the double and triple RESURF devices also increase to about 2 10 12 -3 10 12 cm 2 , respectively [21] .…”

Section: Resurf Technologymentioning

confidence: 99%

“…Fig.5Schematic views of (a) single RESURF LDMOS[19] , (b) double RESURF LDMOS[20] , (c) triple RESURF LDMOS[21] , and (d) local charge-balanced RESURF LDMOS[22,23] .…”

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confidence: 99%

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Review of technologies for high-voltage integrated circuits

Zhang

Zhu

et al. 2022

Tsinghua Sci. Technol.

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High-Voltage power Integrated Circuits (HVICs) are widely used to realize high-efficiency power conversions (e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS (BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage (HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance, and process compatibility with low-voltage circuits. The REduced SURFace field (RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field (ENDIF) and REduced BULk Field (REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors' group, such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

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Section: Resurf Technologymentioning

confidence: 99%

Section: Resurf Technologymentioning

confidence: 99%

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Review of technologies for high-voltage integrated circuits

Zhang

Zhu

et al. 2022

Tsinghua Sci. Technol.

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“…1 shows the structure of a two-zone double-RESURF MOSFET. The double RESURF structure has a top-p region placed on the top of the RESURF region [14]. Since the double-RESURF region is depleted not only from the bottom p-epilayer/RESURF junction but also from the RESURF/ top-p junction, a higher RESURF dose can be employed than in normal RESURF MOSFETs, leading to a lower on-resistance.…”

Section: Introductionmentioning

confidence: 99%

1580-V–40-$\hbox{m}\Omega\cdot \hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC$(\hbox{000}\bar{\hbox{1}})$

Noborio

Suda

Kimoto

2009

IEEE Electron Device Lett.

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Double-reduced-surface-field (RESURF) MOSFETs with N 2 O-grown oxides have been fabricated on the 4H-SiC (0001) face. The double-RESURF structure is effective in reducing the drift resistance, as well as in increasing the breakdown voltage. In addition, by utilizing the 4H-SiC (0001) face, the channel mobility can be increased to over 30 cm 2 /V · s, and hence, the channel resistance is decreased. As a result, the fabricated MOSFETs on 4H-SiC (0001) have demonstrated a high breakdown voltage (V B ) of 1580 V and a low on-resistance (R ON ) of 40 mΩ · cm 2 . The figure-of-merit (V 2 B /R ON ) of the fabricated device has reached 62 MW/cm 2 , which is the highest value among any lateral MOSFETs and is more than ten times higher than the "Si limit." Index Terms-Breakdown voltage, MOSFET, on-resistance, reduced surface field (RESURF), silicon carbide (SiC).

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“…[8][9][10][11] The authors have employed double RESURF structure to reduce the drift resistance. The concept of double RESURF structure 12) is similar to that of ''superjunction'' structure. 13) In our previous work, the fabricated double RESURF MOSFET with doses in RESURF region of below 1 Â 10 13 cm À2 demonstrated a breakdown voltage of 1380 V and an onresistance of 66 m cm 2 .…”

mentioning

confidence: 99%

Improved Performance of 4H-SiC Double Reduced Surface Field Metal–Oxide–Semiconductor Field-Effect Transistors by Increasing RESURF Doses

Noborio

Suda

Kimoto

2008

Appl. Phys. Express

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For further improvement of lateral power devices, 4H-SiC double reduced surface field (RESURF) metal–oxide–semiconductor field-effect transistors (MOSFETs) with high doses in RESURF region have been fabricated and characterized. The drift resistance was decreased and the breakdown voltage was increased with increasing RESURF doses, although breakdown occurs in the oxide when the RESURF doses are too high. The increase of drift resistance in double RESURF MOSFETs at elevated temperature was smaller than that in single RESURF MOSFETs, due to the higher doping concentration in the RESURF region. The fabricated 4H-SiC(0001) double RESURF MOSFETs exhibited a breakdown voltage (VB) of 1540 V and an on-resistance (RON) of 55 mΩ cm2. The figure-of-merit (VB2/RON) of the fabricated device is 43 MW/cm2, which is the highest value compared with those reported in lateral MOSFETs.

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High voltage, high current lateral devices

Cited by 30 publications

References 0 publications

Review of technologies for high-voltage integrated circuits

Review of technologies for high-voltage integrated circuits

1580-V–40-$\hbox{m}\Omega\cdot \hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC$(\hbox{000}\bar{\hbox{1}})$

Improved Performance of 4H-SiC Double Reduced Surface Field Metal–Oxide–Semiconductor Field-Effect Transistors by Increasing RESURF Doses

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