High-voltage compliant, capacitive-load invariant neural stimulation electronics compatible with standard bulk-CMOS integration

A high-voltage compliant neural stimulator with HF wireless power and UHF backscatter communication

“…The driver utilizes an Hbridge front-end based on the CMOS integration-compatible, high-voltage compliant topology presented in [9]. For a PCB implementation, this topology choice simplifies the powermanagement design and mitigates the effects of on-board parasitics on the shape of the stimulus current waveform.…”

“…The stimulator front-end interfaces with an active and return electrode, with large, series blocking capacitors included for safety and to enable post-stimulus charge-balancing via electrode shorting. A discrete version of the CMOS stimulator front-end topology in [9] is implemented in this work to investigate the use of this topology during in vivo trials and to test the ability of WPT to support HV neural stimulation. Subsequently the system is used to identify any challenges related to integrating HV stimulation with WPT and BSC on the same CMOS substrate.…”

An Offset Charge Compensating Biphasic Neuro - stimulation for Faradaic DC-Current Reduction

“…It can be considered as a connection of two Randles circuit which contains tissue resistance (Rt) and two electrode interfaces. The interface is conventionally modeled as a parallel connection of faradaic resistance (Rf) and double-layer capacitor (Cdl) [7]. In this paper, Qt and Qf is defined as the net charge transfer through Rt and Rf respectively, and charge in the Cdl is denoted by Qdl.…”

“…Since using HV processes consumed much power and area [5], there were attempts to design an HV driver which distributes the HV to the multiple MOS stack. There were attempts to use sequential switching [7], but it lacks programmability. The self-adaptive HV driver was proposed in [8,9,10].…”

“…Connecting one electrode node to the supply voltage, the voltage rise caused by pre-existing charge at the electrode induces a countercurrent leakage. It may cause a critical amount of charge mismatch [7]. However, using the alternative DC offset path scheme [11], it can lower the node voltage preventing countercurrent.…”