High throughput pipelined hardware implementation of the KECCAK hash function

Mestiri, Hassen; Kahri, Fatma; Bedoui, Mouna; Bouallègue, Belgacem; Machhout, Mohsen

doi:10.1109/isivc.2016.7894001

Cited by 25 publications

(8 citation statements)

References 2 publications

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“…In the full proposed architecture, we obtain Fmax of 194.50 MHz, utilize 7702 ALMs, achieve the throughput of 28.02 Gbps, 26.46 Gbps, 20.24 Gbps, and 14.01 Gpbs and the efficiency of 3.63 Mbps/ALM, 3.43 Mbps/ALM, 2.62 Mbps/ALM, and 1.82 Mbps/ALM for SHA3-224, SHA3-256, SHA3-384, and SHA3-512, respectively. Compared to [9], we achieve 1.11 times in throughput and 0.67 times in efficiency for SHA3-512. Compared to [13], we achieve 1.86 times in throughput and 0.32 times in efficiency for SHA3-512 mode.…”

Section: Evaluation and Resultsmentioning

confidence: 94%

“…Additionally, a pipeline technique is applied within the RF. This approach, proposed by the authors in [9,10], involves the insertion of registers between the pi and chi functions to reduce critical path delays. In addition to improving performance, the designs in [8,10] also exhibit a high level of flexibility, enabling support for applications with multiple modes of SHA-3.…”

Section: Introductionmentioning

confidence: 99%

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Efficiency System-level SHA-3 Accelerator for IoT

Huynh,

Dang,

Tran

et al. 2023

Preprint

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Edge computing has emerged as a significant computing trend alongside the rapid expansion of the Internet of Things (IoT). Computing operations at the network’s edge offer a solution to the high latency and service overload challenges often associated with cloud computing. Additionally, the Secure Hash Algorithm-3 (SHA-3) plays a crucial role in ensuring data integrity and is implemented for numerous applications in the IoT field. Therefore, integrating the SHA-3 accelerator into edge computing is essential. Moreover, recent studies about SHA-3 have primarily focused on achieving high performance and optimizing resource utilization for SHA-3. However, these studies have overlooked the crucial aspect of data transfer between the external memory and the hash function block, as transfer time plays a significant role. This paper proposes an efficient SHA-3 architecture designed for System-on-Chip (SoC) Field Programmable Gate Array (FPGA) to address the aforementioned challenges and be suitable for real edge computing. The architecture contains three key techniques. First, the harmony of padding and Direct Memory Access (DMA) for managing the data transfer process and enhancing performance efficiency based on Serial Input to Parallel Output (SIPO) and a barrel shifter. Secondly, implementing internal pipelining within the Round Function (RF) to reduce critical path delays and optimize resource utilization. Finally, designing four modes (SHA3-224, SHA3-256, SHA3-384, and SHA3-512) to cater to various applications. Our architecture is implemented and tested on the DE10-Standard Development Kit (Cyclone V SX SoC-5CSXFC6D6F31C6N), which is integrated into the FPGA and is controlled by a Dual-Core ARM Cortex-A9 processor. The result is up to 38.34 Gbps in throughput and 5.61 Mbps/ALM in efficiency for the RF computation, 28.02 Gbps in throughput, and 3.63 Mbps/ALM for the full proposed architecture.

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Section: Evaluation and Resultsmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

Efficiency System-level SHA-3 Accelerator for IoT

Huynh,

Dang,

Tran

et al. 2023

Preprint

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“…On this work [12], the authors propose a pipelined Keccak architecture. The proposed Keccak architecture is implemented on a Xilinx FPGA platform (Virtex-5) and simulated in ModelSim.…”

Section: Related Workmentioning

confidence: 99%

High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor

2020

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Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak algorithm is the winner of the NIST competition for the adoption of the new standard SHA-3 hash algorithm. In this work, we present hardware throughput optimization techniques for the SHA-3 algorithm using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) programming language for all output lengths in the Keccak hash function (224, 256, 384 and 512). Our experiments were performed with the Nios II processor on the FPGA Arria 10 GX (10AX115N2P45E1SG). We applied two architectures, one without custom instruction and one with floating point hardware 2. Finally, we compare the results with other existing similar designs and found that the proposed design with floating point 2 optimizes throughput (Gbps) compared to existing FPGA implementations.

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“…The introduction of SHA-3, with its unique SPONGE construction, aims to enhance cryptographic security and address potential vulnerabilities identified in SHA-1. A hardware implementation of SHA-3 has been explored in various studies [11,12,13,14,15,16,17,18,19,20]. Some studies [11,12] emphasize resource savings by employing the folding mechanism, which allows for the reuse of resources multiple times.…”

Section: Introductionmentioning

confidence: 99%

A multimode SHA-3 accelerator based on RISC-V system

Huynh,

Dang,

Tran

et al. 2024

IEICE Electron. Express

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Nowadays, almost all fields cannot lack security, from the essential encryption/decryption to hash function algorithms. The Secure Hash Algorithm 3 (SHA-3) with four modes, SHA3-224/256/384/512, is a known new hash function due to being more secure than its predecessors, SHA-1 and SHA-2. While hardware implementations of SHA-3 have been extensively studied, the primary focus has often been on optimizing the KECCAK algorithm. This paper introduces an efficient multimode SHA-3 architecture (MS3) featuring configurable buffers and a sub-pipeline KECCAK design. These innovations aim to save resources and boost throughput, respectively. Furthermore, MS3 is integrated with the reduced instruction set computer five (RISC-V) system as a hardware accelerator via the TileLink bus. This integration enables MS3 to communicate with RISC-V for configuration purposes and utilize direct memory access (DMA) for efficient data transfer with memory. Experimental results on the Cyclone IV E platform demonstrate MS3 achieving approximately 500 Mbps throughput across all modes, with DMA achieving a throughput of 540.21 Mbps. Additionally, our design exhibits superior efficiency compared to existing works on Virtex 5, 6, and 7 FPGA platforms.

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High throughput pipelined hardware implementation of the KECCAK hash function

Cited by 25 publications

References 2 publications

Efficiency System-level SHA-3 Accelerator for IoT

Efficiency System-level SHA-3 Accelerator for IoT

High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor

A multimode SHA-3 accelerator based on RISC-V system

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