High Throughput Multidimensional Tridiagonal Systems Solvers on FPGAs

Abstract

This paper presents a design space exploration for synthesizing optimized, high-throughput implementations of multiple multi-dimensional tridiagonal system solvers on FPGAs. Re-evaluating the characteristics of algorithms for the direct solution of tridiagonal systems, we develop a new tridiagonal solver library aimed at implementing high-performance computing applications on Xilinx FPGA hardware. Key new features of the library are (1) the unification of standard state-of-the-art techniques for implementing implicit numerical solvers with a number of novel high-gain optimizations such as vectorization and batching, motivated by multiple multi-dimensional systems common in real-world applications, (2) data-flow techniques that provide application specific optimizations for both 2D and 3D problems, including integration of explicit loops commonplace in real workloads, and (3) the development of a predictive analytic model to explore the design space, and obtain rapid resource and performance estimates. The new library provide an order of magnitude better performance when solving large batches of systems compared to Xilinx's current tridiagonal solver library. Two representative applications are implemented using the new solver on a Xilinx Alveo U280 FPGA, demonstrating over 85% predictive model accuracy. These are compared with a current state-of-the-art GPU library for solving multi-dimensional tridiagonal systems on an Nvidia V100 GPU, analyzing time to solution, bandwidth, and energy consumption. Results show the FPGAs achieving competitive or better runtime performance for a range of multi-dimensional mesh problems compared to the V100 GPU. Additionally, the significant energy savings offered by FPGA implementations, over 30% for the most complex application, are quantified. We discuss the algorithmic trade-offs required to obtain good performance on FPGAs, giving insights into the feasibility and profitability of FPGA implementations.

FPGA Acceleration of Structured-Mesh-Based Explicit and Implicit Numerical Solvers using SYCL

“…Modern HLS tools based work such as [10,11,13,19,21,30,37,38,40] have showcased key workflows and optimizations in synthesizing stencil applications using high-level languages such as C++ and OpenCL on a variety of FPGAs from Xilinx to Intel. Similarly, implicit schemes based solvers such as tridiagonal systems solvers have been implemented in works such as [20,[23][24][25]39] including for multi-dimensional multiple tridiagonal solvers in addition to vendor supplied libraries such as [3]. In our present work, the aim is to investigate how the SYCL programming model can be used to synthesise high-performance implementations of these solvers on Intel FPGAs and showcase the challenges and opportunities to elucidate solutions using this new programming model.…”

“…The best tridiagonal solver algorithms for implementing data-flow optimizations needs to be examined together with the utility of SYCL for their synthesis on Intel FPGAs. We base our investigation and development on recent work [20], again done with Xilinx FPGAs. The work in [20] explores the various algorithms for implementing multi-dimensional tridiagonal solvers on FPGAs, focusing on gaining higher throughput from multiple solvers setup on a multi-dimensional domain.…”

“…We base our investigation and development on recent work [20], again done with Xilinx FPGAs. The work in [20] explores the various algorithms for implementing multi-dimensional tridiagonal solvers on FPGAs, focusing on gaining higher throughput from multiple solvers setup on a multi-dimensional domain. This aligns closely with how industrial workloads utilize tridiagonal solvers, particularly from the financial computing domain, as opposed to the best algorithms and optimizations for a single tridiagonal system solve as found in many other previous work.…”

“…(1) Based on design strategies developed in previous work [19,20], in this paper we develop a generalized workflow for formulating optimized FPGA designs with SYCL, targeting Intel FPGAs for two classes of structured-mesh based solvers: (1) stencil applications based on explicit numerical methods and…”

“…The performance models provided high accuracy with less than 5% model prediction errors for all cases, demonstrating their significant utility for design space explorations. The techniques developed previously in [19,20] were explored in the context of Xilinx FPGAs, the other currently dominant FPGA device in the market. With the present work, we broaden these generalized designs to include features of Intel FPGAs enabling to provide a comprehensive workflow for design-space explorations.…”