High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud

Ober, Micha; Hofmann, Jaco; Sommer, Lukas; Weber, Lukas; Koch, Andreas

doi:10.1109/h2rc49586.2019.00009

Cited by 6 publications

(2 citation statements)

References 5 publications

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“…The work in [36] targets PCs through fully-spatial mapping on FPGA. However, since large PCs cannot be completely spatially mapped, their approach is limited to only small DAGs with fewer than 500 nodes.…”

Section: Fpgamentioning

confidence: 99%

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs

Shah

Meert

Verhelst

2022

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)

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A growing number of applications like probabilistic machine learning, sparse linear algebra, robotic navigation, etc., exhibit irregular data flow computation that can be modeled with directed acyclic graphs (DAGs). The irregularity arises from the seemingly random connections of nodes, which makes the DAG structure unsuitable for vectorization on CPU or GPU. Moreover, the nodes usually represent a small number of arithmetic operations that cannot amortize the overhead of launching tasks/kernels for each node, further posing challenges for parallel execution.To enable energy-efficient execution, this work proposes DAG processing unit (DPU) version 2, a specialized processor architecture optimized for irregular DAGs with static connectivity. It consists of a tree-structured datapath for efficient data reuse, a customized banked register file, and interconnects tuned to support irregular register accesses. DPU-v2 is utilized effectively through a targeted compiler that systematically maps operations to the datapath, minimizes register bank conflicts, and avoids pipeline hazards. Finally, a design space exploration identifies the optimal architecture configuration that minimizes the energy-delay product. This hardwaresoftware co-optimization approach results in a speedup of 1.4×, 3.5×, and 14× over a state-of-the-art DAG processor ASIP, a CPU, and a GPU, respectively, while also achieving a lower energy-delay product. In this way, this work takes an important step towards enabling an embedded execution of emerging DAG workloads.

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Section: Fpgamentioning

confidence: 99%

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs

Shah

Meert

Verhelst

2022

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)

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“…The same accelerator was also used to demonstrate TaPaSCo's portability: As domain experts from the machine learning community usually do not run and maintain FPGA boards in on-premise setups, the accelerator architecture was ported [51] to the reconfigurable cloud, namely the F1 instances found in Amazon's AWS EC2 cloud. As the TaPaSCo architecture is completely platform-independent and TaPaSCo provides suitable platform integration for the F1 instances, the accelerator could be ported without any changes to the core itself.…”

Section: Custom Hdl-based Acceleratorsmentioning

confidence: 99%

The TaPaSCo Open-Source Toolflow

Heinz

Hofmann

Korinth

et al. 2021

J Sign Process Syst

Self Cite

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The integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.

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