High-Throughput H.264/AVC High-Profile CABAC Decoder for HDTV Applications

Yang, Yao-Chang; Guo, Jiun-In

doi:10.1109/tcsvt.2009.2020340

Cited by 25 publications

(1 citation statement)

References 6 publications

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“…For the increased throughput of entropy decoding with low power consumption, several very large-scale integration architecture designs for H.264/AVC context adaptive binary arithmetic coding (CABAC) and context adaptive variable length coding (CAVLC) are proposed. 12,13 Furthermore, many look-up table-based algorithms have been proposed for fast entropy decoding as the software solution with digital signal processors (DSPs). However, DSP-based software solutions need additional improvement for real-time decoding of high-bitrate videos.…”

Section: Introductionmentioning

confidence: 99%

Bitstream decoding processor for fast entropy decoding of variable length coding–based multiformat videos

Sim

2014

Opt. Eng

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We present a bitstream decoding processor for entropy decoding of variable length coding-based multiformat videos. Since most of the computational complexity of entropy decoders comes from bitstream accesses and table look-up process, the developed bitstream processing unit (BsPU) has several designated instructions to access bitstreams and to minimize branch operations in the table look-up process. In addition, the instruction for bitstream access has the capability to remove emulation prevention bytes (EPBs) of H.264/AVC without initial delay, repeated memory accesses, and additional buffer. Experimental results show that the proposed method for EPB removal achieves a speed-up of 1.23 times compared to the conventional EPB removal method. In addition, the BsPU achieves speed-ups of 5.6 and 3.5 times in entropy decoding of H.264/AVC and MPEG-4 Visual bitstreams, respectively, compared to an existing processor without designated instructions and a new table mapping algorithm. The BsPU is implemented on a Xilinx Virtex5 LX330 field-programmable gate array. The MPEG-4 Visual (ASP, Level 5) and H.264/AVC (Main Profile, Level 4) are processed using the developed BsPU with a core clock speed of under 250 MHz in real time.

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Section: Introductionmentioning

confidence: 99%

Bitstream decoding processor for fast entropy decoding of variable length coding–based multiformat videos

Sim

2014

Opt. Eng

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Decoder Hardware Architecture for HEVC

Tikekar¹,

Huang²,

Juvekar³

et al. 2014

Integrated Circuits and Systems

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This chapter provides an overview of the design challenges faced in the implementation of hardware HEVC decoders. These challenges can be attributed to the larger and diverse coding block sizes and transform sizes, the larger interpolation filter for motion compensation, the increased number of steps in intra prediction and the introduction of a new in-loop filter. Several solutions to address these implementation challenges are discussed. As a reference, results for an HEVC decoder test chip are also presented.Acknowledgements The authors gratefully acknowledge the support of Texas Instruments for sponsoring the HEVC decoder test chip project and Taiwan Semiconductor Manufacturing Company (TSMC) University Shuttle program for manufacturing the chip.

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Joint Algorithm-Architecture Optimization of CABAC

Sze

Chandrakasan

2012

J Sign Process Syst

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This paper uses joint optimization of both the algorithm and architecture to enable high coding efficiency in conjunction with high processing speed and low area cost. Specifically, it presents several optimizations that can be performed on Context Adaptive Binary Arithmetic Coding (CABAC), a form of entropy coding used in H.264/AVC, to achieve the throughput necessary for real-time low power high definition video coding. The combination of syntax element partitions and interleaved entropy slices, referred to as Massively Parallel CABAC, increases the number of binary symbols that can be processing in a cycle. Subinterval reordering is used to reduce the cycle time required to process each binary symbol. Under common conditions using the JM12.0 software, the Massively Parallel CABAC, increases the bins per cycle by 2.7 to 32.8x at a cost of 0.25% to 6.84% coding loss compared with sequential single slice H.264/AVC CABAC. It also provides a 2x reduction in area cost, and reduces memory bandwidth. Subinterval reordering reduces critical path by 14% to 22%, while modifications to context selection reduces memory requirement by 67%. This work illustrates that accounting for implementation cost during video coding algorithms design can enable higher processing speed and reduce hardware cost, while still delivering high coding efficiency in the next generation video coding standard.

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High-Throughput H.264/AVC High-Profile CABAC Decoder for HDTV Applications

Cited by 25 publications

References 6 publications

Bitstream decoding processor for fast entropy decoding of variable length coding–based multiformat videos

Bitstream decoding processor for fast entropy decoding of variable length coding–based multiformat videos

Decoder Hardware Architecture for HEVC

Joint Algorithm-Architecture Optimization of CABAC

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