High Throughput FPGA Implementation of LDPC Decoder Architecture for DVB-S2X Standard

Likhobabin, Evgeny; Ovinnikov, Aleksei; Goriushkin, Ruslan; Nikishkin, P. B.; Khokhryakov, Evgeny I.

doi:10.1109/icct56057.2022.9976733

Cited by 2 publications

(2 citation statements)

References 12 publications

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“…Several studies have ventured into the domain of FPGAbased LDPC decoder designs for diverse LDPC codes and communication standards. In the study of Likhobabin et al [35], a highly parallel decoder that leverages Min-Sum decoding was proposed. This decoder demonstrated a throughput of up to 500 Mbps for QC-LDPC codes under the DVB-S2X standard.…”

Section: Related Workmentioning

confidence: 99%

Enhancing Data Communication Performance: A Comprehensive Review and Evaluation of LDPC Decoder Architectures

Subhi,

Al-Doori,

Alani

2023

ISI

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Error Correction Codes (ECCs) stand as a linchpin in ensuring data accuracy in wireless communication. As the landscape of modern communication standards continues to expand, there is a mounting inclination towards efficient ECC technologies, such as Low-Density Parity-Check codes (LDPCs). Distinguished by their near-capacity performance and low computational complexity, LDPCs are increasingly utilized in the successful encoding and decoding of data. This study undertakes an exploration of recent advancements in LDPC research, encompassing the analysis of decoding algorithms, architectures, applications, simulations, real-world implementations, and complexities across various hardware platforms. The central research problem addressed within this work is the identification of the most efficacious LDPC decoder implementation, with an emphasis placed on Field-Programmable Gate Array (FPGA) technology. From the outcomes of this study, the Min-Sum algorithm emerged as the favored choice for LDPC decoding, particularly within FPGA implementations. The selection of this algorithm is attributable to its simplicity and implementation feasibility, thus directly addressing the posed research problem. The inherent simplicity of the Min-Sum algorithm's structure renders it a practical choice for real-world applications. Further, its proficiency in error correction and compatibility with FPGA hardware underscore its potential for augmenting the reliability of data transmission in communication systems. The findings of this study advocate for the Min-Sum algorithm as a valuable asset in LDPC decoding, notably within FPGA implementations. This positions it as a promising candidate for optimizing data communication systems. The selection of FPGA as the implementation platform reaffirms its practicality and relevance in contemporary communication technology, thus offering a comprehensive solution to the identified research problem.

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Section: Related Workmentioning

confidence: 99%

Enhancing Data Communication Performance: A Comprehensive Review and Evaluation of LDPC Decoder Architectures

Subhi,

Al-Doori,

Alani

2023

ISI

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“…The low-density parity check coding was initially proposed by Robert Gallager in [19], and later recalled by MacKay [3,20], and demonstrated that irregular LDPC codes can asymptotically approach the Shannon limit [21] of lossless transmission. In the last decade, LDPC codes have become very popular as a powerful error correction coding method with the possibility of algorithm parallelization that enables the development of hardware codecs with optimized algorithms and very high throughput [22][23][24][25], typically for high-speed industrial communication standards [26,27].…”

Section: Ldpc Coding-preliminariesmentioning

confidence: 99%

Energy-Efficient Raptor-like LDPC Coding Scheme Design and Implementation for IoT Communication Systems

Hyła¹,

Sulek

2023

Energies

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The large number of inexpensive and energy-efficient terminals in IoT systems is one of the emerging elements of the recent landscape of information and communication technologies. IoT nodes are usually embedded systems with limited processing power devices and strict requirements on energy consumption. In this paper, we consider the design and implementation of a part of the IoT communication uplink stack, namely the error correction coding scheme, for energy-efficient operation. We examine how an efficient rate-adaptive coding scheme, namely the Raptor-like (RL) quasi-cyclic (QC) subclass of low-density parity check (LDPC) codes, can be applied. We present an encoding algorithm designed for an embedded CPU; a respective QC-RL-LDPC decoding scheme, based on typical LDPC iterative decoding; and a combined design procedure for construction of the QC-RL-LDPC parity check matrices. Next, we conduct experiments to explore the time intervals for implemented encoding and the goodput of the coding system with incremental redundancy. We provide the statistical results by combining the measured energy consumption of the encoder and the simulated radio transmitter energy consumption. We demonstrate the comparison of normalized energy consumption statistics with the fixed-rate LDPC coding case. As conclusion, we note that under an unknown channel corruption level, the short block QC-RL-LDPC code implemented in the CPU can achieve higher energy efficiency per information bit compared to a fixed-rate LDPC code. Future work will include an extension of the work to nonbinary QC-RL-LDPC coding design.

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High Throughput FPGA Implementation of LDPC Decoder Architecture for DVB-S2X Standard

Cited by 2 publications

References 12 publications

Enhancing Data Communication Performance: A Comprehensive Review and Evaluation of LDPC Decoder Architectures

Enhancing Data Communication Performance: A Comprehensive Review and Evaluation of LDPC Decoder Architectures

Energy-Efficient Raptor-like LDPC Coding Scheme Design and Implementation for IoT Communication Systems

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