High throughput channel tracking for JTRS wireless channel emulation

Lee, Dajung; Matai, Janarbek; Weals, B.T.; Kastner, Ryan

doi:10.1109/fpl.2014.6927410

Cited by 4 publications

(2 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Restructured code typically differs substantially from a software implementation -even one that is highly optimized. A number of studies suggest that restructuring code is an essential step to generate an efficient FPGA design [46,47,15,14,39]. Thus, in order to get an efficient hardware design, the user must write restructured code with the underlying hardware architecture in mind.…”

Section: Restructured Codementioning

confidence: 99%

Parallel Programming for FPGAs

Kastner¹,

Matai²,

Neuendorffer³

2018

Preprint

Self Cite

View full text Add to dashboard Cite

Many people have contributed to making this book happen. Probably first and foremost are the many people who have done research in the area of High-Level Synthesis. Underlying each of the applications in this book are many individual synthesis and mapping technologies which combine to result in high-quality implementations.Many people have worked directly on the Vivado R HLS tool over the years. From the beginning in Jason Cong's research group at UCLA as the AutoPilot tool, to making a commercial product at AutoESL Inc., to widespread adoption at Xilinx, it's taken many hours of engineering to build an effective tool. To Zhiru Zhang, Yiping Fan, Bin Liu, Guoling Han, Kecheng Hao, Peichen Pan, Devadas Varma, Chuck Song, and many others: your efforts are greatly appreciated.The idea for this book originally arose out of a hallway conversation with Salil Raje shortly after Xilinx acquired the AutoESL technology. Much thanks to Salil for his early encouragement and financial support. Ivo Bolsens and Kees Vissers also had the trust that we could make something worth the effort. Thanks to you all for having the patience to wait for good things to emerge. This book would not have been possible without substantial support from the UCSD Wireless Embedded Systems Program. This book grew out of the need to make a hardware design class that could be broadly applicable to students coming from a mix of software and hardware backgrounds. The program provided substantial resources in terms of lab instructors, teaching assistants, and supplies that were invaluable as we developed (and re-developed) the curriculum that eventually morphed into this book. Thanks to all the UCSD 237C students over the years for providing feedback on what made sense, what didn't, and generally acting as guinea pigs over many revisions of the class and this book. Your suggestions and feedback were extremely helpful. A special thanks to the TAs for these classes, notable Alireza Khodamoradi, Pingfan Meng, Dajung Lee, Quentin Gautier, and Armaiti Ardeshiricham; they certainly felt the growing pains a lot more than the instructor.Various colleagues have been subjected to early drafts of the book, including Zhiru Zhang, Mike Wirthlin, Jonathan Corbett. We appreciate your feedback.

show abstract

Section: Restructured Codementioning

confidence: 99%

Parallel Programming for FPGAs

Kastner¹,

Matai²,

Neuendorffer³

2018

Preprint

Self Cite

View full text Add to dashboard Cite

show abstract

“…A field‐programmable gate array channel emulator was proposed in [20] with 200 MHz bandwidth to realise a 3D non‐stationary geometry‐based stochastic model. A programmable and extensible channel emulator was presented in [21] to track a 250 MHz wide digital baseband data stream to accommodate wideband frequency hopping. In [22], a real‐time digital baseband emulator was presented for baseband signals up to 30 MHz.…”

Section: Introductionmentioning

confidence: 99%