High-Throughput, Area-Efficient Architecture of 2-D Block FIR Filter Using Distributed Arithmetic Algorithm

Kumar, Prashant; Shrivastava, Prabhat Chandra; Tiwari, Manish; Mishra, G. R.

doi:10.1007/s00034-018-0897-2

Cited by 18 publications

(19 citation statements)

References 10 publications

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“…At each systolic stage, a set of

1

delayed inputs is required to generate a block of input. The input pixels at

the stage is represented by

, which is given in matrix form as 11 :

…”

Section: Background: Block-based Design and Symmetry Of 2-d Fir Filtersmentioning

confidence: 99%

“…To facilitate parallelism, we further decompose the input pixel matrix

and coefficient vector by a factor of s. The input pixel matrix

is decomposed into

sub matrices represented as

of dimension

, and also the coefficient vector

of dimension

;

01

Equation (4) is modified as 11

…”

Section: Background: Block-based Design and Symmetry Of 2-d Fir Filtersmentioning

confidence: 99%

“…Kumar et al . 11 , 12 recently proposed block-based 2-D FIR and IIR filter architectures using DA with a memory-sharing approach but did not discuss the symmetry of coefficients. DA-based FIRAs are described in, 13 , 14 and the review of DA methods for cost-effective and efficient FIRAs is summarized.…”

Section: Introductionmentioning

confidence: 99%

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Implementation of distributed arithmetic-based symmetrical 2-D block finite impulse response filter architectures

Chowdari Ch,

Seventline

2023

F1000Res

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Background: This paper presents an efficient two-dimensional (2-D) finite impulse response (FIR) filter using block processing for two different symmetries. Architectures for a general filter (without symmetry) and two symmetrical filters (diagonal and quadrantal symmetry) are implemented. The proposed architectures need fewer multipliers because of the symmetry of the filter coefficients. Methods: A distributed arithmetic (DA)- based multiplication method is used in the proposed architecture. A dual-port memory-based lookup table (DP-MLUT) is used in the multiplication instead of lookup-table (LUT) to reduce the area and power of the FIR filter. The filter's throughput is increased by using block processing. Memory reuse and memory sharing methods are introduced, which reduces the need for many registers and hence the circuit complexity. The architectures are written in Verilog Hardware Description Language and synthesized using Genus Synthesis tool-19.1 in 45nm technology with a generic library of Cadence vendor constraints. The synthesis tool generates the area, delay, and power reports. Power consumption of architectures is calculated with an image size of 64 X 64 and at 20 MHz frequency. Results: Compared to existing architectures, the synthesis results show improvements in power, area, area delay product (ADP), and power delay product (PDP). The proposed MLUT-based 2-D block Quadrantal Symmetry Filter (QSF) for length 8 with block size 4 consumes 58.94% less power, occupies 59.5% less area, 48.44% less ADP and 47.78% less PDP compared to best existing methods. Conclusions: A novel DA-based 2-D block FIR filter architecture with various symmetries is realized. Symmetry is incorporated into the filter coefficients to minimize the number of multipliers. The LUT size is optimized by odd multiples or even multiples storage techniques. Also, the overall area of the architecture is decreased by DP-LUT-based multipliers. The proposed filter architecture is area-power-efficient. It is best suited for applications that have fixed coefficients.

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“…At each systolic stage, a set of

1

delayed inputs is required to generate a block of input. The input pixels at

the stage is represented by

, which is given in matrix form as 11 :

…”

Section: Background: Block-based Design and Symmetry Of 2-d Fir Filtersmentioning

confidence: 99%

“…To facilitate parallelism, we further decompose the input pixel matrix

and coefficient vector by a factor of s. The input pixel matrix

is decomposed into

sub matrices represented as

of dimension

, and also the coefficient vector

of dimension

;

01

Equation (4) is modified as 11

…”

Section: Background: Block-based Design and Symmetry Of 2-d Fir Filtersmentioning

confidence: 99%

See 1 more Smart Citation

Implementation of distributed arithmetic-based symmetrical 2-D block finite impulse response filter architectures

Chowdari Ch,

Seventline

2023

F1000Res

View full text Add to dashboard Cite

show abstract

“…It specifically targets the sum of products computation, predominately featuring in many important digital signal processing (DSP) filtering and frequency transformation functions. It can be used to implement a wide variety of applications, such as signal processing (Lu, Duan, Halak, & Kazmierski, 2019), filters (Kalaiyarasi & Reddy, 2019;Kumar, Shrivastava, Tiwari, & Mishra, 2019), control systems (Chan, Moallem, & Wang, 2004, 2007, system-on-chip (SoC) applications (Khawam, Arslan, & Westall, 2004) and discrete cosine transforms (Pan, Shams, & Bayoumi, 1999;Sowmya & Mathew, 2019;Yu & Swartzlander Jr., 2001). All these implementations utilise lookup tables to store certain aspects of the computation.…”

Section: Lookup Table Reconfigurationmentioning

confidence: 99%

Improving functional density of time-critical applications using hardware-based dynamic reconfiguration and bitstream specialisation

Roux

Schoor

Vuuren

2019

SACJ

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The dynamic reconfiguration of an FPGA has many advantages, but the overhead from the process reduces the functional density of applications. Functional density is an indication of the composite benefits a reconfigured application obtains above its generic counterpart and measures the computational throughput per unit hardware resources. Typically, only quasi-static applications obtain a functional density advantage by dynamically reconfiguring its parameters. Contributing to the functional density reduction of applications with tight time constraints is the overhead to generate a new configuration, and the time it takes to load it onto the device. Normally these applications have to reuse their hardware numerous times between configurations before obtaining a functional density advantage. The most promising reconfiguration method to improve functional density with minimal hardware reuse was one that extracts certain characteristics from the bitstream and then implements a bitstream specialiser that generates new hardware at bit-level while the device is being reconfigured. While it was shown that this method allows reconfiguration of an application in real-time, its effect on functional density was not determined. This paper will show that a significant increase in functional density can be achieved for applications where reconfiguration is required before the next execution cycle of the application.

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“…The hardware implementation complexity of a traditional 2‐D FIR filter is high due to its 2‐D coefficients multiplication. For lessening the hardware implementation complexity, several techniques have been proposed [10–16], such as McClellan transformation technique [10,11], matrix decomposition based separable technique [8,12], ℓ 1 norm based sparse traditional 2‐D FIR filter design technique [13] and the very recently proposed polyphase decomposition and farrow structure based technique [14,15]. The McClellan transformation technique can achieve considerable hardware complexity reduction at the cost of obviously larger equivalent filter size [12].…”

Section: Introductionmentioning

confidence: 99%

Coefficients Quantization for Separable Two‐Dimensional FIR Filter

Wang

Cheng

et al. 2021

IEEJ Transactions Elec Engng

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A separable two‐dimensional (2‐D) finite impulse response (FIR) filter can be implemented using an efficient parallel structure. The continuous coefficient separable 2‐D FIR filter has already been well studied. In this study, the quantization of the coefficients of a separable 2‐D FIR filter is addressed for the first time. Two (iterative) schemes [two‐step integer linear programming algorithm (2‐step‐integer‐LP) and two‐step integer linear programming neighborhood search algorithm (2‐step‐integer‐LP‐neighbor)] for quantizing the coefficients are proposed, which have the same core idea: fixing some coefficients and optimally quantizing the other coefficients. Simulation experiment is conducted to verify the effectiveness of the proposed quantization schemes. The experimental results reveal that the two schemes both outperform the direct rounding method in terms of the design error. 2‐Step‐integer‐LP performs slightly better than 2‐step‐integer‐LP‐neighbor. However, the former may not work, in some case, due to the large number of optimization variables. © 2021 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

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High-Throughput, Area-Efficient Architecture of 2-D Block FIR Filter Using Distributed Arithmetic Algorithm

Cited by 18 publications

References 10 publications

Implementation of distributed arithmetic-based symmetrical 2-D block finite impulse response filter architectures

Implementation of distributed arithmetic-based symmetrical 2-D block finite impulse response filter architectures

Improving functional density of time-critical applications using hardware-based dynamic reconfiguration and bitstream specialisation

Coefficients Quantization for Separable Two‐Dimensional FIR Filter

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