High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion

Abstract

Aiming at protection of high speed data, field programmable gate array (FPGA)-based advanced encryption standard (AES) design is proposed here. Deep investigation into the logical operations of AES with regard to FPGA architectures leads to two efficient pipelining structures for the AES hardware implementation. The two design options allow users to make a trade-off among speed, resource usage and power consumption. In addition, a new key expansion scheme is proposed to address the potential issues of existing key expansion scheme used in AES. The proposed key expansion scheme with additional nonlinear operations increases the complexity of cracking keys by up to 2 (N − 1) times for N-round AES. The proposed design is evaluated on various FPGA devices and is compared with several existing AES implementations. In terms of both throughput and throughput per slice, the proposed design can overcome most existing designs and achieves a throughput of 75.9 Gbps on a latest FPGA device. Two parallel implementations of the proposed design can meet the real-time encryption/decryption demand for 100 Gbps data rate. Furthermore, the proposed AES design is implemented on the Zynq xc7z020 FPGA platform, demonstrating its application to image encryption.

Performance Evaluation of Lightweight Advanced Encryption Standard Hardware Implementation

“…Comparisons of the result of synthesis with existing non-pipelined implementations is shown in Table III. In the XC7VX690T device, the proposed LAES is 78.79% better in terms of throughput and an improvement of 1.37% in performance efficiency compared to [30] although the proposed design has a higher area by 76.34% in slice usage. Similarly compared to [25], although there is an increase in area by 22.96% in slice utilization, there is an improvement of 41.71% in throughput and 15.26% in performance efficiency.…”

“…Similarly compared to [25], although there is an increase in area by 22.96% in slice utilization, there is an improvement of 41.71% in throughput and 15.26% in performance efficiency. In XC6VLX240T device, the proposed LAES improved the throughput by 202.98% and 65.11% compared to [24] and [30] respectively. Although the throughput in [25] is higher by 3.94%, the proposed LAES is better in terms of performance efficiency by 361.3% and has a lesser in area utilization by 79.05%.…”

“…The throughput in [25] is higher using XC6SLX150 but in terms of area and performance efficiency, the proposed LAES is better by 84.42% and 444.53% respectively. In XC4VLX60 device, there is an increase in throughput by 42.28% and 6.97% compared to [30] and [25] respectively. The comparison of existing pipelined implementation to various FPGA devices to the synthesis result of proposed LAES is presented in Table IV.…”

FPGA based highly efficient MISTY1 architecture

“…The design and optimization of cryptographic algorithms have been studied in detail keeping in view the application requirements for low area, high speed or achieving a trade-off between area and speed [2,3,4,5,6,7,8,9,10,11]. For low area design, the commonly adopted methods include re-utilization of logic blocks and s-boxes optimization [2,3,4,5,6,7].…”

“…The compact MISTY1, however are highly unsuitable for high speed applications having low throughput values. Contrary to area-efficient design schemes, encryption algorithms including AES, KASUMI, CAMELLIA and MISTY1 employ RAMs/LUTs/combinational logic to substitute s-boxes using pipe-lined architecture for high speed implementations [7,8,9,10,11]. It is found that the non-optimized high-speed architectures implementing straight-forward pipelines require large area thus reducing the efficiency [7,11].…”