High throughput and resource efficient AES encryption/decryption for SANs

Wang, Yi; Ha, Yajun

doi:10.1109/iscas.2016.7527453

Cited by 20 publications

(5 citation statements)

References 6 publications

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“…AES-EncDec architecture. Wang and Ha achieved a throughput of 78.22 Gbps using a fully-pipelined architecture at the cost of high usage of all types of FPGA components: flip flops, LUTs, Block RAM, DSP [18]. This is an example of a high-throughput design with high resource usage.…”

Section: Discussionmentioning

confidence: 99%

DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs

Grycel¹,

Walls²

2019

Preprint

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Advanced Encryption Standard (AES) implementations on Field Programmable Gate Arrays (FPGA) commonly focus on maximizing throughput at the cost of utilizing high volumes of FPGA slice logic. High resource usage limits systems' abilities to implement other functions (such as video processing or machine learning) that may want to share the same FPGA resources. In this paper, we address the shared resource challenge by proposing and evaluating a low-area, but high-throughput, AES architecture. In contrast to existing work, our DSP/RAM-Based Low-CLB Usage (DRAB-LOCUS) architecture leverages block RAM tiles and Digital Signal Processing (DSP) slices to implement the AES Sub Bytes, Mix Columns, and Add Round Key sub-round transformations, reducing resource usage by a factor of 3 over traditional approaches. To achieve area-efficiency, we built an inner-pipelined architecture using the internal registers of block RAM tiles and DSP slices. Our DRAB-LOCUS architecture features a 12-stage pipeline capable of producing 7.055 Gbps of interleaved encrypted or decrypted data, and only uses 909 Look Up tables, 593 Flip Flops, 16 block RAMs, and 18 DSP slices in the target device. CCS CONCEPTS• Hardware → Hardware accelerators; High-speed input / output.

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Section: Discussionmentioning

confidence: 99%

DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs

Grycel¹,

Walls²

2019

Preprint

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“…The AES-GCM algorithm and its enhancement for nonce misuse protection in the AES-GCM-SIV algorithm show the evolution of AE algorithms due to effectiveness of attacks on security algorithms. Besides, many researchers have provided the optimization of the AES-GCM algorithm by efficient utilizing area [27]- [29] and by increasing throughput [30], [31]. Meanwhile, a Parallel Cipher-based Message Authentication Code (PCMAC) algorithm was introduced for fulfilling the high throughput requirements of modern-day computation [32].…”

Section: Related Workmentioning

confidence: 99%

Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application

Pirzada

Murtaza

et al. 2020

IEEE Access

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High-speed data communication is becoming essential for many applications, including satellite communication. The security algorithms associated with the communication of information are also required to have high-speed for coping up with the communication speed. Moreover, the Authenticated Encryption (AE) algorithms provide high-speed communication and security services include data encryption, authentication, and integrity. The AE algorithms are available with serial and parallel architectures; among them, the Galois Counter Mode (GCM) algorithm has a parallel architecture. The Synthetic Initialization Vector (SIV) mode in the AES-GCM-SIV algorithm provides the nonce misuse protection using the GCM algorithm. Besides, reduced data throughput is provided using the AES-GCM-SIV algorithm as compared to the AES-GCM algorithm. This work introduced a parallel algorithm with re-keying and randomization of the initialization vector for high data throughput, nonce misuse protection, and side-channel attack protection. The implementation of the proposed algorithm is performed on Field Programmable Gate Array (FPGA) and it's compared with the FPGA implementations of AES-GCM, AES-GCM-SIV, and recently introduced algorithms. The optimization of the proposed algorithm and security analysis is presented for space application using different optimizations and a combination of optimizations.

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“…Thulasimani and Madheswaran proposed an efficient hardware architecture of the AES encryption based on FPGA and VHDL, which showed high efficiency and energy saving. Wang and Ha presented the FPGA‐based masked AES with area optimization for Storage Area Network (SAN), and in another work of the aforementioned authors, they developed a high throughput and resource efficient AES encryption/decryption on FPGA for SAN to fully exploit the dedicated resources of modern FPGAs. Rahimunnisa et al presented a folded architecture of the AES algorithm with parallel operations, and they achieved a high throughput of the AES algorithm.…”

Section: Related Workmentioning

confidence: 99%

Implementation and optimization of a data protecting model on the Sunway TaihuLight supercomputer with heterogeneous many‐core processors

Chen

Fei

et al. 2018

Concurrency and Computation

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With the rapid development of information technology, the security of massive amounts of digital data has attracted huge attention in recent years. The Advanced Encryption Standard (AES) algorithm and the Security Hash Algorithm 3 (SHA3) are extensively used as cryptographic algorithms for protecting the security of information. The Sunway TaihuLight, with massive heterogeneous many-core SW26010 processors, has the peak performance of over 100 PFlops. To achieve high efficiency of data encryption/decryption and guarantee the data integrity for large-scale applications, this paper proposes a fast and secure data protecting model using the parallel AES algorithm and the SHA3 on the Sunway TaihuLight. According to the particular computing architecture and memory hierarchy of the Sunway TaihuLight, we propose a fine-grained software design for the data protecting model to fully exploit the parallelism and properly arranges the data on the Sunway. Furthermore, we propose optimization strategies for the parallel AES algorithm of the data protecting model. It is proved that our data protecting model has high security, good scalability, and excellent encryption/decryption efficiency on the Sunway. Our data protecting model achieves a high throughput of 269.95 Gbits/s, and the optimized parallel AES algorithm achieves 511.28 Gbits/s on the Sunway. KEYWORDSadvanced encryption standard (AES), heterogeneous many-core processor, parallelism, security hash algorithm 3 (SHA3), Sunway TaihuLight supercomputer INTRODUCTION MotivationIn recent years, many network platforms, such as micro-blog, forums, and e-commerce sites, have become increasingly popular. Large amount of digital data is generated and stored in the internet. As the activity of internet users progressively increases, we are faced with the risk of security and confidentiality of massive digital information. In addition, the growing number of incidences of data leakage leads serious impact and losses to the internet users, which makes the data security become the hot point and a major concern of the society. It is extremely urgent to figure out a way to provide a reliable and safe environment for internet users.Using the cryptographical technology is one of the key methods to ensure the security of digital data. In cryptography, the block cipher has strong applicability and security. It executes encryption and decryption on a set of fixed-size data blocks using a symmetric key. The Advanced Encryption Standard (AES) 1 is a block cipher extensively used by enterprises and organizations for protecting the security of information. However, the traditional AES encryption/decryption is a computationally intensive task, which leads to the inefficiency of encrypting/decrypting large-scale digital data. In addition, the traditional AES algorithm is unable to meet the demand of protecting massive data efficiently. Users cannot accept too much time spent on data encryption/decryption. Normally, the AES algorithm takes a 16-byte data block as input and performs several rounds o...

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High throughput and resource efficient AES encryption/decryption for SANs

Cited by 20 publications

References 6 publications

DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs

DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs

Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application

Implementation and optimization of a data protecting model on the Sunway TaihuLight supercomputer with heterogeneous many‐core processors

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